Abstract: A method for system power management includes steps of detecting power output of plural power-supplying units (PSUs) and power consumption of plural computing node, so as to indirectly obtain real-time auxiliary power consumption of an auxiliary unit and continuously update maximum auxiliary power consumption; when one of the PSUs is malfunctioned, renewing the maximum sum of the power output of the other PSUs, and applying the difference of the renewed maximum sum of the power outputs and the maximum auxiliary power consumption as a first sum of the node power consumptions of the computing nodes; finally, according to the first sum of the node power consumptions, cutting down the power consumption of at least one of the computing nodes to a first node power consumption.

Abstract: Embodiments relate to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first gate electrode; and a second dielectric material adjacent to the other 3 sides of the first gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first gate electrode.

Abstract: A method includes providing a substrate, wherein the substrate includes a conductive feature in a top portion of the substrate; forming a buffer layer over the substrate; forming a dielectric layer over the buffer layer; performing a first etching process to form an opening in the dielectric layer, thereby exposing a top surface of the buffer layer; and performing a second etching process to extend the opening downwardly into the buffer layer, thereby exposing a top surface of the conductive feature, wherein the performing of the second etching process includes laterally enlarging a footing profile of the opening.

Abstract: A method of forming a semiconductor device includes forming a material layer over a substrate and forming a first trench in the material layer, forming a conformal capping layer along sidewalls of the first trench, forming a second trench in the material layer while the capping layer is disposed along sidewalls of the first trench and forming a conductive feature within the first trench and the second trench.

Abstract: A touch screen is disclosed that includes conductive elements in a display area and connecting traces for routing the conductive elements to other locations. The connecting traces can be routed underneath or over existing opaque structures in the display area, instead of in border areas adjacent to the display area, to minimize the effect of the connecting traces on the display aperture ratio. The lengths and/or widths of these connecting traces as well as the number of parallel connecting traces used to connect to a particular element can be selected to balance the load on the drive and/or sense circuitry and on display pixels caused by the connecting traces.

Abstract: The present disclosure provides a semiconductor structure having a semiconductor layer; a gate with a conductive portion and a sidewall spacer; an interlayer dielectric (ILD) surrounding the sidewall spacer; and a nitrogen-containing protection layer, positioning at least on the top surface of the conductive portion of the gate. A top surface of the conductive portion and a top surface of the sidewall spacer are substantially coplanar. The nitrogen-containing protection layer is not covering the sidewall surface of the sidewall spacer. The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a metal gate structure having a conductive portion and a sidewall spacer surrounded by a first ILD; forming a protection layer over the metal gate structure, and the protection layer is formed to cover at least the conductive portion of the metal gate structure; and forming a second ILD over the metal gate structure.

Abstract: A camera system including a telephoto lens module is provided. The telephoto lens module includes a first image sensor, a first assembly, and a second assembly. The first assembly includes a first driving mechanism and a reflecting member connected to the first driving mechanism. The first driving mechanism is configured to drive the reflecting member to rotate around a first axis and a second axis. The second assembly is disposed between the first assembly and the first image sensor, including a second driving mechanism and a first lens. The second driving mechanism is configured to drive the first lens to move along a third axis. The first, second, and third axes are not parallel to each other. When light enters the telephoto lens along the first axis, light is reflected by the reflecting member and through the first lens along the third axis to the first image sensor.

Abstract: A transparent film is used with a projector which emits a projected light. The transparent film includes a transparent substrate; a light-scattering layer disposed at an upstream position of the transparent substrate with respect to the projected light, and including a plurality of microstructures configured to scatter the projected light; and a light-blocking layer disposed at an upstream position of the light-scattering layer with respect to the projected light, and including a plurality of separate light-blocking units, which are configured to partially block the projected light and partially allow the projected light to reach the light-scattering layer.

Abstract: In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device includes a memory cell, a bit line couple to the memory cell, a voltage supply line coupled to the memory cell, a control circuitry. The control circuitry is configured to charge a voltage supply line while the voltage supply line is electrically isolated from a bit line. A portion of the charge is transferred from the voltage supply line to the bit line. The voltage supply line is recharged while the voltage supply line is electrically isolated from the bit line storing the transferred portion of the charge. The memory cell is accessed using the recharge on the voltage supply line.

Abstract: A method includes forming a first dielectric layer over a semiconductor fin protruding from a substrate, forming a second dielectric layer over the first dielectric layer, then removing a portion of the semiconductor fin to form a first recess defined by portions of the first dielectric layer, followed by removing that portions of the first dielectric layer that define the first recess. Thereafter, the method proceeds to forming an epitaxial source/drain (S/D) feature in the first recess, removing the second dielectric layer to form a second recess that is disposed between the epitaxial S/D feature and remaining portions of the first dielectric layer, and subsequently forming a silicide layer over the epitaxial S/D feature, such that the silicide layer wraps around the epitaxial S/D feature.

Abstract: An optical lens includes a first lens group and a second lens group arranged in order from a first side to a second side, and an aperture stop disposed between the first lens group and the second lens group. The optical lens satisfies the condition of LT/IMH<4.7, where IMH is semi-diagonal image height on an image plane, and LT is a distance along an optical axis between a surface of a first lens of the first lens group facing the first side and a surface of a last lens of the second lens group facing the second side. The first lens is closest to the first side among the first lens group, and the last lens is closest to the second side among the second lens group.

Abstract: A device housing includes a front face, a rear face and a bent side face connecting the front face with the rear face, and the rear face includes a reserved region and an assembling region connected with the reserved region. The flexible screen component covers the front face, the bent side face and the assembling region, and has a display region and an extending layer protruding from the display region. Two ends of the display region are assembled and fitted with two sides of the reserved region, respectively. The retractable device is assembled in the device housing, and connected with the extending layer.

Abstract: The application discloses an electronic device including a motherboard and a housing structure. The motherboard has a first surface and a second surface. The housing structure includes a first casing, a first cushion, a second casing, and a second cushion. The first casing has at least one first fixing member. The first cushion covers the first surface, is accommodated in the first casing and has at least one first through hole. The second casing has at least one second fixing member. The second cushion covers the second surface, is accommodated in the second casing and has at least one second through hole. A peripheral edge of the first cushion is attached to a peripheral edge of the second cushion, and the first fixing member may be fixed to the second fixing member through the first through hole and the second through hole.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate having a first surface and a second surface opposite thereto, wherein the substrate includes a wiring structure, and a first semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The package further includes a second semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are separated by a molding material. A first hole and a second hole are formed on the second surface of the substrate. Finally, a frame is disposed over the first surface of the substrate, wherein the frame surrounds the first semiconductor die and the second semiconductor die.

Abstract: A method of and apparatus for wirelessly collecting and transmitting environmental condition information received from one or more environmental monitoring sensors located in and around a property of homes, buildings or structures. The environmental monitoring sensors communicates the conditions to a Property Management Communication Hub (e.g., a signal hub) The systems, apparatuses, and methods are Self-Contained Property Management System (‘SCPMS’) In one embodiment, a property management method is performed/executed by one or more algorithm implemented processor within the Property Management Communication Hub. The method comprises receiving an encoded event alert from a wireless sensor, encoding the event information, and transmitting the encoded event information to a remote location by a communication module configured to communicate using a wireless communication method.

Abstract: A device includes a semiconductive fin, a first gate stack, a second gate stack, an insulating structure, and a spacer. The semiconductive fin extends along a first direction. The first gate stack extends along a second direction and across the semiconductive fin. The first gate stack includes a high-? dielectric layer and a gate electrode. The high-? dielectric layer is over the semiconductive fin. The gate electrode is over the high-? dielectric layer. The second gate stack extends along the second direction and is substantially aligned with the first gate stack along the second direction. The insulating structure is between the first gate stack and the second gate stack. The high-? dielectric layer is spaced apart from the insulating structure. The spacer extends along a sidewall of the first gate stack and beyond a first sidewall of the insulating structure that faces the first gate stack.

Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a gate dielectric layer, a work function layer, and a conductive filling over the work function layer. The semiconductor device structure also includes a dielectric layer covering the fin structure. The dielectric layer is in direct contact with the conductive filling.