Patents by Inventor An G. Chu
An G. Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11163568Abstract: An approach is provided in which a system writes a set of data into a register file entry that includes a first memory array and a second memory array. The register file entry also includes a set of first write ports corresponding to the first memory array and a set of second write ports corresponding to the second memory array. The system configures a selection bit based on determining that a selected one of the set of first write ports is utilized to store the set of data in the first memory array. In turn, the system reads the set of data out of the first memory array based on the configured selection bit.Type: GrantFiled: September 6, 2018Date of Patent: November 2, 2021Assignee: International Business Machines CorporationInventors: Saiful Islam, Sam G. Chu, Dung Q. Nguyen, Binglong Zhang, Howard Levy, David R. Terry, Steven J. Battle
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Patent number: 11144323Abstract: Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent execution of one or more threads in a multiple slice processor. In one embodiment, a system is disclosed including a plurality of dispatch queues which receive instructions from one or more threads and an even number of parallel execution slices, each parallel execution slice containing a register file. A routing network directs an output from the dispatch queues to the parallel execution slices and the parallel execution slices independently execute the one or more threads.Type: GrantFiled: November 7, 2019Date of Patent: October 12, 2021Assignee: International Business Machines CorporationInventors: Sam G. Chu, Markus Kaltenbach, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Dung Q. Nguyen, Brian W. Thompto
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Publication number: 20200081713Abstract: An approach is provided in which a system writes a set of data into a register file entry that includes a first memory array and a second memory array. The register file entry also includes a set of first write ports corresponding to the first memory array and a set of second write ports corresponding to the second memory array. The system configures a selection bit based on determining that a selected one of the set of first write ports is utilized to store the set of data in the first memory array. In turn, the system reads the set of data out of the first memory array based on the configured selection bit.Type: ApplicationFiled: September 6, 2018Publication date: March 12, 2020Inventors: Saiful Islam, Sam G. Chu, Dung Q. Nguyen, Binglong Zhang, Howard Levy, David R. Terry, Steven J. Battle
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Publication number: 20200073668Abstract: Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent execution of one or more threads in a multiple slice processor. In one embodiment, a system is disclosed including a plurality of dispatch queues which receive instructions from one or more threads and an even number of parallel execution slices, each parallel execution slice containing a register file. A routing network directs an output from the dispatch queues to the parallel execution slices and the parallel execution slices independently execute the one or more threads.Type: ApplicationFiled: November 7, 2019Publication date: March 5, 2020Inventors: Sam G. Chu, Markus Kaltenbach, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Dung Q. Nguyen, Brian W. Thompto
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Patent number: 10564691Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.Type: GrantFiled: November 3, 2017Date of Patent: February 18, 2020Assignee: International Business Machines CorporationInventors: Steven J. Battle, Owen Chiang, Sam G. Chu, Saiful Islam, Dung Q. Nguyen, David R. Terry, Eula A. Tolentino
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Patent number: 10545762Abstract: Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent execution of one or more threads in a multiple slice processor. In one embodiment, a system is disclosed including a plurality of dispatch queues which receive instructions from one or more threads and an even number of parallel execution slices, each parallel execution slice containing a register file. A routing network directs an output from the dispatch queues to the parallel execution slices and the parallel execution slices independently execute the one or more threads.Type: GrantFiled: November 7, 2017Date of Patent: January 28, 2020Assignee: International Business Machines CorporationInventors: Sam G. Chu, Markus Kaltenbach, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Dung Q. Nguyen, Brian W. Thompto
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Patent number: 10296337Abstract: Methods and apparatus for preventing premature reads from a general purpose register (GPR) including receiving an instruction comprising a source operand identifying a source GPR entry; setting a read-enabled flag based on a value in a particular entry of a source ready vector; if the read-enabled flag indicates data in the source GPR entry is ready for reading, dispatching the received instruction, including performing a read operation of the data in the source GPR entry; and if the read-enabled flag indicates data in the source GPR entry is not ready for reading, dispatching the received instruction without performing a read operation of the data in the source GPR entry.Type: GrantFiled: March 21, 2016Date of Patent: May 21, 2019Assignee: International Business Machines CorporationInventors: Steven J. Battle, Owen Chiang, Sam G. Chu, Saiful Islam, Dung Q. Nguyen, David R. Terry, Eula A. Tolentino
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Patent number: 10209757Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.Type: GrantFiled: November 2, 2017Date of Patent: February 19, 2019Assignee: International Business Machines CorporationInventors: Steven J. Battle, Owen Chiang, Sam G. Chu, Saiful Islam, Dung Q. Nguyen, David R. Terry, Eula A. Tolentino
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Publication number: 20180088653Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.Type: ApplicationFiled: November 2, 2017Publication date: March 29, 2018Inventors: STEVEN J. BATTLE, OWEN CHIANG, SAM G. CHU, SAIFUL ISLAM, DUNG Q. NGUYEN, DAVID R. TERRY, EULA A. TOLENTINO
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Publication number: 20180074565Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.Type: ApplicationFiled: November 3, 2017Publication date: March 15, 2018Inventors: STEVEN J. BATTLE, OWEN CHIANG, SAM G. CHU, SAIFUL ISLAM, DUNG Q. NGUYEN, DAVID R. TERRY, EULA A. TOLENTINO
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Publication number: 20180067746Abstract: Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent execution of one or more threads in a multiple slice processor. In one embodiment, a system is disclosed including a plurality of dispatch queues which receive instructions from one or more threads and an even number of parallel execution slices, each parallel execution slice containing a register file. A routing network directs an output from the dispatch queues to the parallel execution slices and the parallel execution slices independently execute the one or more threads.Type: ApplicationFiled: November 7, 2017Publication date: March 8, 2018Inventors: Sam G. Chu, Markus Kaltenbach, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Dung Q. Nguyen, Brian W. Thompto
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Patent number: 9870045Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.Type: GrantFiled: February 17, 2016Date of Patent: January 16, 2018Assignee: International Business Machines CorporationInventors: Steven J. Battle, Owen Chiang, Sam G. Chu, Saiful Islam, Dung Q. Nguyen, David R. Terry, Eula A. Tolentino
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Patent number: 9870229Abstract: Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent execution of one or more threads in a multiple slice processor. In one embodiment, a system is disclosed including a plurality of dispatch queues which receive instructions from one or more threads and an even number of parallel execution slices, each parallel execution slice containing a register file. A routing network directs an output from the dispatch queues to the parallel execution slices and the parallel execution slices independently execute the one or more threads.Type: GrantFiled: September 29, 2015Date of Patent: January 16, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sam G. Chu, Markus Kaltenbach, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Dung Q. Nguyen, Brian W. Thompto
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Patent number: 9870039Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.Type: GrantFiled: December 15, 2015Date of Patent: January 16, 2018Assignee: International Business Machines CorporationInventors: Steven J. Battle, Owen Chiang, Sam G. Chu, Saiful Islam, Dung Q. Nguyen, David R. Terry, Eula A. Tolentino
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Publication number: 20170269936Abstract: Methods and apparatus for preventing premature reads from a general purpose register (GPR) including receiving an instruction comprising a source operand identifying a source GPR entry; setting a read-enabled flag based on a value in a particular entry of a source ready vector; if the read-enabled flag indicates data in the source GPR entry is ready for reading, dispatching the received instruction, including performing a read operation of the data in the source GPR entry; and if the read-enabled flag indicates data in the source GPR entry is not ready for reading, dispatching the received instruction without performing a read operation of the data in the source GPR entry.Type: ApplicationFiled: March 21, 2016Publication date: September 21, 2017Inventors: STEVEN J. BATTLE, OWEN CHIANG, SAM G. CHU, SAIFUL ISLAM, DUNG Q. NGUYEN, DAVID R. TERRY, EULA A. TOLENTINO
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Patent number: 9720696Abstract: Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent execution of one or more threads in a multiple slice processor. In one embodiment, a system is disclosed including a plurality of dispatch queues which receive instructions from one or more threads and an even number of parallel execution slices, each parallel execution slice containing a register file. A routing network directs an output from the dispatch queues to the parallel execution slices and the parallel execution slices independently execute the one or more threads.Type: GrantFiled: September 30, 2014Date of Patent: August 1, 2017Assignee: International Business Machines CorporationInventors: Sam G. Chu, Markus Kaltenbach, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Dung Q. Nguyen, Brian W. Thompto
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Publication number: 20170168544Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.Type: ApplicationFiled: February 17, 2016Publication date: June 15, 2017Inventors: STEVEN J. BATTLE, OWEN CHIANG, SAM G. CHU, SAIFUL ISLAM, DUNG Q. NGUYEN, DAVID R. TERRY, EULA A. TOLENTINO
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Publication number: 20170168539Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.Type: ApplicationFiled: December 15, 2015Publication date: June 15, 2017Inventors: STEVEN J. BATTLE, OWEN CHIANG, SAM G. CHU, SAIFUL ISLAM, DUNG Q. NGUYEN, DAVID R. TERRY, EULA A. TOLENTINO
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Patent number: 9639418Abstract: The embodiments herein generate parity check data which serves as parity-on-parity. Stated differently, the parity check data can be used to determine if parity data stored in a memory element has been corrupted. For example, after generating the parity data, a computing system may set the parity check data depending on whether there is an even or odd number of logical ones (or logical zeros) in the parity data. Thus, when the parity data is read out of the memory element, if the parity data does not include the same number of even or odd bits, the parity check data indicates to the computing system that the parity data is corrupted. In one embodiment, to reduce the likelihood that the parity check data becomes corrupted, the computing system stores this data in hardened latches which are less susceptible to soft errors than other types of memory elements.Type: GrantFiled: September 1, 2015Date of Patent: May 2, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joshua W. Bowman, Sam G. Chu, Dhivya Jeganathan, Cliff Kucharski, Dung Q. Nguyen, David R. Terry
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Publication number: 20170109093Abstract: Method and system for writing data into a register entry of a processing unit is provided. A logic unit issues an instruction for writing result data into a register entry. At least one functional unit coupled to the logic unit receives the instruction and provides partial result data to be written into the register entry and information regarding the partial result data. A logic circuit coupled to the register entry receives the information regarding the partial result data and writes the partial result data into at least one portion of the register entry based on the received information, the at least one portion of the register entry being determined based on the received information.Type: ApplicationFiled: October 14, 2015Publication date: April 20, 2017Inventors: Sam G. CHU, David A. HRUSECKY, Dung Q. NGUYEN, Jose A. PAREDES, David R. TERRY, Brian W. THOMPTO