Patents by Inventor An Hsu

An Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MULTIFUNCTIONAL SINGLE WAFER SOAKING-SPINNING-CLEANING DEVICE AND WAFER PROCESSING METHOD
    Publication number: 20240293848
    Abstract: The present invention discloses a multifunctional single wafer soaking-spinning-cleaning device and a wafer processing method. The method includes a device providing step, a first lifting step, a wafer placing step, a second lifting step, a soaking step, and a third lifting steps, and a spinning cleaning step. The device providing step includes providing a multifunctional single wafer immersion and spin cleaning device, the device has a spin drive device, a wafer turntable, and a wafer receiving tray. A soaking tank is formed on the wafer receiving tray, and a watertight contact gasket is disposed on the wafer receiving tray to contact the wafer water-tightly such that in the soaking step, an appropriate water level of the liquid medicine can be accumulated to fully soak the wafer.
    Type: Application
    Filed: March 10, 2023
    Publication date: September 5, 2024
    Inventors: Li-tso HUANG, Hsiu-kai CHANG, Chin-yuan WU, Ming-che HSU
  • Transporting Apparatus with Shock Absorbing Elements
    Publication number: 20240294202
    Abstract: The present disclosure provides a transporting apparatus. The transporting apparatus can include the following components: a first frame support configured to support an object; a second frame support configured to roll the transporting apparatus and to move relative to the first frame support; and a plurality of shock absorbing elements positioned between the first frame support and the second frame support.
    Type: Application
    Filed: May 13, 2024
    Publication date: September 5, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yueh-Sheng HSU, Liang-Kun Zhu
  • SEMICONDUCTOR PACKAGE STRUCTURE
    Publication number: 20240297120
    Abstract: A semiconductor package structure includes a first redistribution layer, a first semiconductor die, a second semiconductor die, a bridge structure, and a plurality of conductive bumps. The first semiconductor die and the second semiconductor die are disposed over the first redistribution layer. The bridge structure is disposed under the first redistribution layer. The first semiconductor die is electrically coupled to the second semiconductor die through the first redistribution layer and the bridge structure. The conductive bumps are disposed under the first redistribution layer and are coupled to the first redistribution layer. The bridge structure is disposed between at least two of the conductive bumps.
    Type: Application
    Filed: January 9, 2024
    Publication date: September 5, 2024
    Inventors: Wei-Yu CHEN, Yi-Lin TSAI, Nai-Wei LIU, Shih-Chin LIN, Wen-Sung HSU
  • ONON Sidewall Structure for Memory Device and Method for Making the Same
    Publication number: 20240296890
    Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.
    Type: Application
    Filed: May 13, 2024
    Publication date: September 5, 2024
    Inventors: Chen-Ming Huang, Wen-Tuo Huang, Yu-Hsiang Yang, Yu-Ling Hsu, Wei-Lin Chang, Chia-Sheng Lin, ShihKuang Yang, Yu-Chun Chang, Hung-Ling Shih, Po-Wei Liu, Shih-Hsien Chen
  • SUBSTRATE ASSEMBLY AND ELECTRONIC DEVICE INCLUDING THE SAME
    Publication number: 20240297132
    Abstract: A substrate assembly and an electronic device are provided. The substrate assembly includes a substrate, a first metal layer, a second metal layer, a third conductive layer, and an insulating layer. The first metal layer is disposed on the substrate. The second metal layer is disposed on the substrate. The third conductive layer is disposed between the first metal layer and the second metal layer, wherein the third conductive layer overlaps with a part of the first metal layer and overlaps a part of the second metal layer. The insulating layer is disposed between the first metal layer and the second metal layer and has an opening through which the part of the first metal layer and the second metal layer are electrically connected with each other.
    Type: Application
    Filed: May 3, 2024
    Publication date: September 5, 2024
    Inventors: Maggy HSU, Pierre CHEN
  • PACKAGING METHOD
    Publication number: 20240297101
    Abstract: A packaging method, includes: providing a continuous multi-package structure, which includes a lead frame and a molding layer formed on the lead frame, wherein the lead frame includes a plurality of recesses formed on a bottom surface on a side of the lead frame opposite to the molding layer; forming a coating layer on the bottom surface, to cover the bottom surface and the recesses on the bottom surface; and mechanically cutting the continuous multi-package structure through the recesses, to separately form a plurality of packaging units, wherein in each of the packaging units, an exposed portion of the lead frame exposed in the recesses includes a step shape.
    Type: Application
    Filed: April 27, 2023
    Publication date: September 5, 2024
    Inventors: Yu-Lin Yang, Ming-Chih Hsu, Chun-Hao Chang
  • ELECTRONIC APPARATUS
    Publication number: 20240297168
    Abstract: The disclosure provides an electronic apparatus. The electronic apparatus includes an insulator, a driving unit, an electronic unit, and a circuit unit. The driving unit is overlapped with the insulator. The electronic unit is overlapped with the insulator. The circuit unit is electrically connected to the driving unit. The driving unit receives a signal from the circuit unit and drives the electronic unit.
    Type: Application
    Filed: May 14, 2024
    Publication date: September 5, 2024
    Applicant: Innolux Corporation
    Inventors: Tang Chin Hung, Chin-Lung Ting, Chung-Kuang Wei, Ker-Yih Kao, Tong-Jung Wang, Chih-Yung Hsieh, Hao Jung Huang, I-Yin Li, Chia-Chi Ho, Yi Hung Lin, Cheng-Hsu Chou, Chia-Ping Tseng
  • PACKAGE STRUCTURE WITH A BARRIER LAYER
    Publication number: 20240297138
    Abstract: Package structures and methods for manufacturing the same are provided. The package structure includes a first substrate and through vias formed through the first substrate. The package further includes redistribution layers formed over the first substrate and connected to the through vias and a first pillar layer formed over the redistribution layers. The package further includes a first barrier layer formed over the first pillar layer and a first cap layer formed over the first barrier layer. The package further includes an underfill layer formed over the redistribution layers and surrounding the first pillar layer, the first barrier layer, and the first cap layer. In addition, the first barrier layer has a first protruding portion laterally extending outside a first sidewall surface of the first pillar layer and a second sidewall surface of the first cap layer.
    Type: Application
    Filed: May 13, 2024
    Publication date: September 5, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hung CHEN, Yu-Nu HSU, Chun-Chen LIU, Heng-Chi HUANG, Chien-Chen LI, Shih-Yen CHEN, Cheng-Nan HSIEH, Kuo-Chio LIU, Chen-Shien CHEN, Chin-Yu KU, Te-Hsun PANG, Yuan-Feng WU, Sen-Chi CHIANG
  • RECYCLING METHOD OF LITHIUM IRON PHOSPHATE BATTERY
    Publication number: 20240297356
    Abstract: The present application provides a recycling method of a lithium iron phosphate battery. The method comprises the following steps: i) providing a first powder comprising lithium iron phosphate battery waste; ii) removing copper and aluminum from the first powder to obtain a second powder, iii) dissolving the second powder obtained in step ii) in nitric acid to obtain a solution; iv) adding carbonic acid in the solution obtained in step iii) and separating a lithium carbonate precipitate; and v) removing a remaining solution of step iv) by vacuum distillation to obtain a ferric nitrate crystal.
    Type: Application
    Filed: June 20, 2023
    Publication date: September 5, 2024
    Applicant: UWin Resource Regeneration Inc.
    Inventors: Ching-Hsiang HSU, Jia-Hao HU
  • POROUS PARTICLES
    Publication number: 20240295068
    Abstract: Provided is a novel water repellent agent in which a biodegradable polyester is used. In the water repellent agent, porous particles having the biodegradable polyester as a main component are contained.
    Type: Application
    Filed: May 13, 2024
    Publication date: September 5, 2024
    Applicants: DAIKIN INDUSTRIES, LTD., OSAKA UNIVERSITY
    Inventors: Ryo AKUTA, Masahiro HIGASHI, Yosuke KISHIKAWA, Yu-I HSU, Hiroshi UYAMA
  • VACUUM PROCESSING APPARATUS
    Publication number: 20240297058
    Abstract: A vacuum processing apparatus including a vacuum processing unit embracing a vacuum vessel into which a wafer to be processed is transferred and processed; a lock chamber into which the wafer is transferred; an atmospheric transfer unit embracing an atmospheric transfer chamber maintained at atmospheric pressure and inside which the wafer is transferred; and a wafer preserving container for stacking a processed wafer. The wafer preserving container is provided inside with an exhaust port which is placed behind the opening, in front of the stacking space, and in an upper and a lower edge regions relative to the stacking space and exhausts gas in the stacking space to outside and a manifold which is placed behind the stacking space, towards the opening between the upper edge region and the lower edge region, and has gas outlets to supply certain gas into the stacking space.
    Type: Application
    Filed: March 15, 2022
    Publication date: September 5, 2024
    Inventors: Chen Pin HSU, Masatsugu FUJITA, Satoshi YAMAMOTO, Masakazu ISOZAKI
  • System and method of fileless malware detection and non-transitory computer readable medium
    Patent number: 12079338
    Abstract: The present disclosure provides a system and a method of fileless malware detection, and the method of the fileless malware detection includes steps as follows. The execution of the writable section in the memory is intercepted; the executable code corresponding to the execution is extracted from the writable section; whether the executable code is malicious is analyzed.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: September 3, 2024
    Assignee: National Central University
    Inventors: Fu-Hau Hsu, Teng-Chuan Hsiao, Chia-Hao Lee
  • Display panel and manufacturing method thereof
    Patent number: 12080543
    Abstract: A display panel includes a substrate, a first metal layer, and a first insulating layer, an oxide semiconductor layer, a second insulating layer, a second metal layer, a third insulating layer, and a third metal layer stacked on each other sequentially. The first insulating layer includes a first region and a second region adjacent to the first region, and a thickness of the second region is less than a thickness of the first region. A projection of at least a portion of the oxide semiconductor layer projected on the substrate overlaps with a projection of the first metal layer projected on the substrate. The third metal layer is connected to the first metal layer through a third via hole, and the third via hole is extended through the first insulating layer and the third insulating layer.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: September 3, 2024
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Yuanpeng Chen, Yuanjun Hsu
  • Techniques for modifying component carrier or layer configuration in multi-subscription wireless communications
    Patent number: 12081464
    Abstract: Aspects described herein relate to communicating with multiple cells based on two separate subscriptions stored at the UE in a dual subscription dual standby (DSDS) mode, switching to communicate with the multiple cells in a dual subscription dual active (DSDA) mode, transmitting, to at least one of the multiple cells and based on a number of component carriers allowed for a subscription being exceeded by switching to communicate in the DSDA mode, assistance information to indicate a threshold amount of component carriers for the UE, and transmitting, to at least one of the multiple cells and based on the number of component carriers allowed for the subscription being exceeded by switching to communicate in the DSDA mode, a channel quality indicator (CQI) value for one or more cells of the multiple cells to request deactivation of one or more component carriers with, or release of, the one or more cells.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: September 3, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Kuo-Chun Lee, Arvind Vardarajan Santhanam, Reza Shahidi, Qingxin Chen, Liangchi Hsu, Cheol Hee Park, Mona Agrawal, Hemanth Kumar Rayapati, Sridhar Bandaru
  • Systems and methods for in-situ Marangoni cleaning
    Patent number: 12080567
    Abstract: In an embodiment, a method includes: immersing a wafer in a bath within a cleaning chamber; removing the wafer out of the bath through a solvent and into a gas within the cleaning chamber; determining a parameter value from the gas; and performing remediation within the cleaning chamber in response to determining that the parameter value is beyond a threshold value.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: September 3, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Chun Hsu, Shu-Yen Wang, Chui-Ya Peng
  • Laser device and light guide member used with the same
    Patent number: 12080989
    Abstract: The laser device includes a substrate, a laser element disposed on the substrate for emitting a laser light ray, a light guide member disposed on the substrate, and a wavelength conversion layer. The light guide member is light-transmissible and thermally conductive, and has at least one reflection surface for reflecting the laser light ray from the laser element so as to change travelling direction of the laser light ray. The wavelength conversion layer converts wavelength of the laser light ray from the light guide member to result in a laser beam, and contacts the light guide member so that heat from the wavelength conversion layer is transferred to the substrate through the light guide member.
    Type: Grant
    Filed: August 11, 2023
    Date of Patent: September 3, 2024
    Assignee: Xiamen Sanan Optoelectronics Technology Co., Ltd.
    Inventors: Hui Chen, Junpeng Shi, Xinglong Li, Chi-Wei Liao, Weng-Tack Wong, Chih-Wei Chao, Chen-ke Hsu
  • Dually derivatized chitosan nanoparticles and methods of making and using the same for gene transfer in vivo
    Patent number: 12076418
    Abstract: Provided herein is chitosan-derivative nanoparticle comprising chitosan functionalized with a cationic amino acid and a hydrophilic polyol; and methods of making and using same, e.g., for gene delivery in vivo.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: September 3, 2024
    Assignee: ENGENE, INC.
    Inventors: Jun Gao, Eric Hsu, Anthony Cheung
  • Epitaxial backside contact
    Patent number: 12080766
    Abstract: A semiconductor device structure according to the present disclosure includes a source feature and a drain feature, at least one channel structure extending between the source feature and the drain feature, a gate structure wrapped around each of the at least one channel structure, a semiconductor layer over the gate structure, a dielectric layer over the semiconductor layer, a doped semiconductor feature extending through the semiconductor layer and the dielectric layer to be in contact with the source feature, a metal contact plug over the doped semiconductor feature, and a buried power rail disposed over the metal contact plug.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: September 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chia-Hung Chu, Tsungyu Hung, Hsu-Kai Chang, Ding-Kang Shih, Keng-Chu Lin, Pang-Yen Tsai, Sung-Li Wang, Shuen-Shin Liang
  • Antenna module
    Patent number: 12080943
    Abstract: An antenna module disposed on a substrate having a first and a second surface opposite to each other includes a microstrip line, a first radiator, a ground radiator and a ground plane. The microstrip line, the first radiator and the ground radiator are disposed on the first surface. The microstrip line includes a first and a second end opposite to each other. The first end includes a first feeding end. The first radiator is connected to the second end of the microstrip line. The ground radiator surrounds the microstrip line and the first radiator and has a first opening and two opposite grounding ends. The first end of the microstrip line is located in the first opening. A gap is formed between each grounding end and the first feeding end. The ground plane is disposed on the second surface. The ground radiator is connected to the ground plane.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: September 3, 2024
    Assignee: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Tse-Hsuan Wang, Chih-Fu Chang, Chao-Hsu Wu, Shih-Keng Huang, Hau Yuen Tan
  • Electronic package
    Patent number: 12080466
    Abstract: An electronic package is provided and includes an electronic element connected to a plurality of inductor circuits embedded in an insulator of a package substrate by fan-out conductive copper pillars, and at least one shielding layer non-electrically connected to the inductor circuits, where the shielding layer includes a plurality of line segments not connected to each other, such that the shielding layer shields the inductor circuits, thereby achieving the electrical requirements of high-current products while improving the inductance value and quality factor.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: September 3, 2024
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventor: Che-Wei Hsu