Patents by Inventor An-Hung Lin

An-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12105355
    Abstract: A wide-angle lens assembly includes a first lens, a second lens, a third lens, a fourth lens, and a fifth lens. The first lens is a meniscus lens with refractive power and includes a convex surface facing an object side and a concave surface facing an image side. The second lens is with refractive power. The third lens is with positive refractive power. The fourth lens is with refractive power. The fifth lens is with positive refractive power and includes a convex surface facing the image side. The first lens, the second lens, the third lens, the fourth lens, and the fifth lens are arranged in order from the object side to the image side along an optical axis.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: October 1, 2024
    Assignees: Sintai Optical (Shenzhen) Co., Ltd., Asia Optical Co., Inc.
    Inventors: Chia-Hung Sun, Tsan-Haw Lee, Yu-Wen Tai, Shu-Hung Lin
  • Patent number: 12105937
    Abstract: In one example, an electronic device may include a display screen defining a plurality of display regions. Further, the electronic device may include a camera to capture an image of an operator of the electronic device. Furthermore, the electronic device may include a controller operatively coupled to the camera and the display screen. The controller may detect an orientation of the operator's face with respect to the display screen using the captured image. Further, the controller may determine a first display region of the plurality of display regions corresponding to the detected orientation of the operators face. Furthermore, the controller may activate the first display region to position a cursor of a pointing device within the first display region.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: October 1, 2024
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Yi-Chien Lin, Chih-Hung Lin, Ling-Yu Wu, Chih-Shiuan Lee
  • Patent number: 12107045
    Abstract: A method includes: disposing a first conductive segment; disposing a first conductive via above the first conductive segment; disposing a first conductive line above the first conductive via; and disposing a second conductive segment electrically coupled to the first conductive line through a third conductive segment, the first conductive segment, and the first conductive via.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: October 1, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Hung Shen, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Wei-Cheng Lin
  • Patent number: 12108412
    Abstract: A method for uplink transmission performed by a UE is provided. The method includes: receiving a first configured grant configuration that allocates a first PUSCH duration; receiving a second configured grant configuration that allocates a second PUSCH duration, wherein the second PUSCH duration overlaps with the first PUSCH duration; obtaining a first HARQ process ID for the first PUSCH duration, then determining whether a first configured grant timer associated with the first HARQ process ID is running; obtaining a second HARQ process ID for the second PUSCH duration, then determining whether a second configured grant timer associated with the second HARQ process ID is running; and selecting one of the first PUSCH duration and the second PUSCH duration for an uplink transmission based on whether the first configured grant timer is running and whether the second configured grant timer is running.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: October 1, 2024
    Assignee: Hannibal IP LLC
    Inventors: Heng-Li Chin, Chia-Hung Wei, Wan-Chen Lin, Yu-Hsin Cheng, Chie-Ming Chou
  • Patent number: 12108680
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to the MTJ and extended to overlap a top surface of the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is adjacent to the top electrode and the MTJ and on the second IMD layer and a top surface of the cap layer is higher than a top surface of the first IMD layer.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: October 1, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Hung-Yueh Chen, Yu-Ping Wang
  • Publication number: 20240316852
    Abstract: A mold assembly has a pressing mold, a shunt cone, and a mold cap. The shunt cone is disposed in the pressing mold to define a conical pressing channel. The shunt cone has a body, an inlet channel, and an outlet channel. The body has a conical cone portion. The inlet channel has an extension height from a top of shunt cone being higher than an extension height of the inlet channel from the top of the shunt cone. The mold cap is attached to a bottom of the pressing mold and has a lower mold cavity to allow the cone portion to extend into the lower mold cavity and to define a conical shaped connection channel. The connection channel communicates with the pressing channel, and a material input channel is defined in the mold cap and communicating with the connection channel.
    Type: Application
    Filed: June 12, 2023
    Publication date: September 26, 2024
    Inventors: Min Hung Chen, Fang-Yun Lin, You-Hung Lu
  • Publication number: 20240315615
    Abstract: A detection element of biological subcutaneous features and a wearable device thereof are provided. The element for detecting biological subcutaneous features has a substrate, a light-detecting semiconductor chip, a grid structure, and a cover. The light-detecting semiconductor chip is located on the substrate for detecting red light or near-infrared light signals. The grid structure including a plurality of opaque light-absorbing blocking walls is located on the light-detecting semiconductor chip for blocking side light and increasing the proportion of near-vertical incident light. The cover is located on the grid structure and serves as a protection lid. The wearable device for detecting biological subcutaneous features has more than one light source of red light or near-infrared light and a plurality of detection elements. The arrangement of the opaque light-absorbing blocking walls that are parallel to each other are substantially parallel to the light-emitting directions of the light source.
    Type: Application
    Filed: March 19, 2024
    Publication date: September 26, 2024
    Inventors: Kai-Hung CHENG, Ku-Cheng LIN, Chun-Min LIN, Ke-Wei LIU
  • Publication number: 20240317926
    Abstract: A zwitterionic resin is manufactured by a manufacturing method which includes the following steps. A first thermal process is performed on a first crosslinking agent and a choline having hydroxyl group or amino group to form a first mixture, in which the first crosslinking agent includes an isocyanate group. A second thermal process is performed on the first mixture, a second crosslinking agent, a chain extender, and an amino acid to form the zwitterionic resin, in which the chain extender includes a polyol.
    Type: Application
    Filed: May 30, 2024
    Publication date: September 26, 2024
    Inventors: Chen-Shou HSU, Sun-Wen JUAN, Chun-Hung LIN
  • Publication number: 20240319590
    Abstract: Optical devices and methods of manufacture are presented in which a first mask is utilized for multiple purposes. Some methods include depositing a first mask over a support material, forming a concave surface in the support material through the first mask, and bonding the first mask to a first bonding layer over an optical interposer.
    Type: Application
    Filed: March 20, 2023
    Publication date: September 26, 2024
    Inventors: Yu-Hung Lin, Yu-Yi Huang, Chih-Hao Yu, Yu-Ting Yen, Shih-Peng Tai
  • Publication number: 20240321765
    Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.
    Type: Application
    Filed: June 6, 2024
    Publication date: September 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Cheng-Chieh Hsieh, Hsiu-Jen Lin, Hui-Jung Tsai, Hung-Yi Kuo, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin, Chun-Ti Lu, Chung-Ming Weng
  • Publication number: 20240322042
    Abstract: A semiconductor device includes a substrate, a dielectric region, a first fin structure, a second fin structure, a plurality of conductive regions, a first conductive rail and a conductive structure. The dielectric region is situated on the substrate. The first fin structure protrudes from the substrate and the dielectric region. The second fin structure protrudes from the substrate and the dielectric region, and extends parallel to the first fin structure. The conductive regions are situated on the dielectric region. The first conductive rail is situated within the dielectric region, and electrically connected to a first conductive region of the plurality of conductive regions. Opposite sides of the first conductive rail face the first fin structure and the second fin structure, respectively. The conductive structure penetrates through the substrate and formed under the first conductive rail, and is electrically connected to the first conductive rail.
    Type: Application
    Filed: May 23, 2024
    Publication date: September 26, 2024
    Inventors: CHIH-LIANG CHEN, LEI-CHUN CHOU, JACK LIU, KAM-TOU SIO, HUI-TING YANG, WEI-CHENG LIN, CHUN-HUNG LIOU, JIANN-TYNG TZENG, CHEW-YUEN YOUNG
  • Publication number: 20240321767
    Abstract: The reflectance of a low-reflectance alignment mark is increased by coating the alignment mark with a high-reflectance film layer. This improves the strength of the light signal and reduces variation in the light signal.
    Type: Application
    Filed: June 7, 2024
    Publication date: September 26, 2024
    Inventors: Tzu-Hao Yeh, Kuan-Jung Chen, Tsung-Lin Lee, Shiuan-Jeng Lin, Hung-Lin Chen
  • Publication number: 20240322056
    Abstract: An optical device includes a photoelectric conversion layer, an underlying layer, an anti-reflection layer, and a plurality of meta units. The underlying layer is disposed on the photoelectric conversion layer. The anti-reflection layer is disposed on the underlying layer. The meta units are disposed above the photoelectric conversion layer, in which each of the meta units includes a top portion and a bottom portion, and a projection of the bottom portion on the photoelectric conversion layer is within a projection of the top portion on the photoelectric conversion layer.
    Type: Application
    Filed: March 21, 2023
    Publication date: September 26, 2024
    Inventors: Shin-Hong KUO, Kai-Hao CHANG, Po-Hsiang WANG, Han-Lin WU, Hung-Jen TSAI
  • Publication number: 20240321661
    Abstract: A method includes forming a reconstructed package substrate, which includes placing a plurality of substrate blocks over a carrier, encapsulating the plurality of substrate blocks in an encapsulant, planarizing the encapsulant and the plurality of substrate blocks to reveal redistribution lines in the plurality of substrate blocks, and forming a redistribution structure overlapping both of the plurality of substrate blocks and encapsulant. A package component is bonded over the reconstructed package substrate.
    Type: Application
    Filed: May 30, 2024
    Publication date: September 26, 2024
    Inventors: Chen-Shien Chen, Kuo-Ching Hsu, Wei-Hung Lin, Hui-Min Huang, Ming-Da Cheng, Mirng-Ji Lii
  • Publication number: 20240321642
    Abstract: A method of fabricating a semiconductor device includes forming, over a substrate, alternating layers of a first semiconductor layer formed of a first semiconductor material and a second semiconductor layer formed of a second semiconductor material, the first semiconductor layers including a first, a second, and a third sub-layers; patterning the alternating layers of the first and the second semiconductor layers to form stacks of the alternating layers; and exposing, under etch conditions, lateral edges of the alternating layers to an etchant to selectively etch recesses in the lateral edges of the first, the second, and the third sub-layers, such that a first lateral depth of the first sub-layer is greater than a second lateral depth of the second sub-layer, and the second lateral depth of the second sub-layer is greater than a third lateral depth of the third sub-layer.
    Type: Application
    Filed: June 4, 2024
    Publication date: September 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chung-Shu Wu, Tze-Chung Lin, Shih-Chiang Chen, Hsiu-Hao Tsao, Chun-Hung Lee
  • Publication number: 20240321798
    Abstract: An electronic package is provided and includes a carrier for carrying electronic components. Electrical contact pads of the carrier for planting solder balls are connected with a plurality of columnar conductors, and the conductors are electrically connected to a circuit portion in the carrier. By connecting a plurality of conductors with a single electrical contact pad, structural stress can be distributed and breakage of the circuit portion can be prevented.
    Type: Application
    Filed: March 12, 2024
    Publication date: September 26, 2024
    Applicant: SILICONWARE PRECISION INDUST RIES CO., LT D.
    Inventors: Chi-Ren Chen, Po-Yung Chang, Pei-Geng Weng, Yuan-Hung Hsu, Chang-Fu Lin, Don-Son Jiang
  • Publication number: 20240320559
    Abstract: A language processing method includes following steps. An initial dataset including initial phrases and initial intent labels about the initial phrases is obtained. A first intent classifier is trained with the initial dataset. Augmented phrases are produced corresponding to the initial phrases by sentence augmentation. First predicted intent labels about the augmented phrases and first confidence levels of the first predicted intent labels are generated by the first intent classifier. The augmented phrases are classified into augmentation subsets according to comparisons between the first predicted intent labels and the initial intent labels and according to the first confidence levels. A second intent classifier is trained according to a part of the augmentation subsets by curriculum learning. The second intent classifier is configured to distinguish an intent of an input phrase within a dialogue.
    Type: Application
    Filed: March 22, 2024
    Publication date: September 26, 2024
    Inventors: Yu-Shao PENG, Yu-De LIN, Sheng-Hung FAN
  • Publication number: 20240321993
    Abstract: A nanowire transistor includes a channel structure on a substrate, a gate structure on and around the channel structure, a source/drain structure adjacent to two sides of the gate structure, and a contact plug connected to the source/drain structure. Preferably, the source/drain structure includes graphene and the contact plug further includes a silicide layer on the source/drain structure, a graphene layer on the silicide layer, and a barrier layer on the graphene layer.
    Type: Application
    Filed: May 31, 2024
    Publication date: September 26, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Kuang Hsieh, Shih-Hung Tsai, Ching-Wen Hung, Chun-Hsien Lin
  • Publication number: 20240321780
    Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a molded semiconductor device, a first redistribution structure, and conductive vias. The molded semiconductor device comprises a sensor die with a first surface and a second surface opposite the first surface, wherein the sensor die has an input/output region and a sensing region at the first surface. The first redistribution structure is disposed on the first surface of the sensor die, wherein the first redistribution structure covers the input/output region and exposes the sensing region, and the first redistribution structure comprises a conductive layer having a redistribution pattern and a ring structure. The redistribution pattern is electrically connected with the sensor die. The ring structure surrounds the sensing region and is separated from the redistribution pattern, wherein the ring structure is closer to the sensing region than the redistribution pattern.
    Type: Application
    Filed: June 4, 2024
    Publication date: September 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Huang, Chih-Hao Chang, Po-Chun Lin, Chun-Ti Lu, Zheng-Gang Tsai, Shih-Wei Chen, Chia-Hung Liu, Hao-Yi Tsai, Chung-Shi Liu
  • Patent number: 12100642
    Abstract: An electronic package is provided and includes an electronic element, an intermediary structure disposed on the electronic element, and a heat dissipation element bonded to the electronic element through the intermediary structure. The intermediary structure has a flow guide portion and a permanent fluid combined with the flow guide portion so as to be in contact with the electronic element, thereby achieving a preferred heat dissipation effect and preventing excessive warping of the electronic element or the heat dissipation element due to stress concentration.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: September 24, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yu-Lung Huang, Chee-Key Chung, Chang-Fu Lin, Yuan-Hung Hsu