Patents by Inventor An-Jhih Su

An-Jhih Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200335438
    Abstract: Device, package structure and method of forming the same are disclosed. The device includes a die encapsulated by an encapsulant, a conductive structure aside the die, and a dielectric layer overlying the conductive structure. The conductive structure includes a through via in the encapsulant, a redistribution line layer overlying the through via, and a seed layer overlying the redistribution line layer. The dielectric layer includes an opening, wherein the opening exposes a surface of the conductive structure, the opening has a scallop sidewall, and an included angle between a bottom surface of the dielectric layer and a sidewall of the opening is larger than about 60 degrees.
    Type: Application
    Filed: July 8, 2020
    Publication date: October 22, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Wei Chen, An-Jhih Su, Li-Hsien Huang
  • Patent number: 10811394
    Abstract: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Wei-Yu Chen, Ying-Ju Chen, Tsung-Shu Lin, Chin-Chuan Chang, Hsien-Wei Chen, Wei-Cheng Wu, Li-Hsien Huang, Chi-Hsi Wu, Der-Chyang Yeh
  • Patent number: 10804247
    Abstract: A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film is electrically connected to the first ground bump.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hua Yu, An-Jhih Su, Jing-Cheng Lin, Po-Hao Tsai
  • Patent number: 10797038
    Abstract: An embodiment is a method including bonding a first package to a first set of conductive pads of a second package with a first set of solder joints, testing the first package for defects, heating the first set of solder joints by directing a laser beam at a surface of the first package based on testing the first package for defects, after the first set of solder joints are heated, removing the first package, and bonding a third package to the first set of conductive pads of the second package.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Shing-Chao Chen, Ching-Hua Hsieh, Chung-Shi Liu, Der-Chyang Yeh, Ming-Da Cheng
  • Patent number: 10796927
    Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Chen-Hua Yu, Chi-Hsi Wu, Der-Chyang Yeh, An-Jhih Su, Wei-Yu Chen
  • Publication number: 20200303332
    Abstract: Semiconductor devices and methods of forming are provided. A molding compound extends along sidewalls of a first die and a second die. A redistribution layer is formed over the first die, the second die, and the molding compound. The redistribution layer includes a conductor overlying a gap between the first die and the second die. The conductor is routed at a first angle over an edge of the first die. The first angle is measured with respect to a straight line that extends along a shortest between the first die and the second die, and the first angle is greater than 0.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Inventors: Hsien-Wei Chen, An-Jhih Su, Tsung-Shu Lin
  • Publication number: 20200300893
    Abstract: The present disclosure provides a probe card device and a conductive probe thereof. The conductive probe includes a metallic pin, an outer electrode, and a dielectric layer. The metallic pin includes a middle segment, a first connecting segment and a second connecting segment respectively extending from two opposite ends of the middle segment, and a first contacting segment and a second contacting segment respectively extending from the first connecting segment and second contacting segment along two opposite directions away from the middle segment. At least part of the outer electrode corresponds in position to the middle segment and is arranged adjacent to the first connecting segment. The dielectric layer is sandwiched between and entirely separates the metallic pin and the outer electrode, so that the outer electrode, the dielectric layer, and the metallic pin are jointly configured to generate a capacitance effect.
    Type: Application
    Filed: January 2, 2020
    Publication date: September 24, 2020
    Inventors: WEN-TSUNG LEE, KAI-CHIEH HSIEH, CHAO-HUI TSENG, WEI-JHIH SU
  • Patent number: 10784207
    Abstract: A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Wei-Cheng Wu
  • Patent number: 10784248
    Abstract: A package includes a first device die, and a first encapsulating material encapsulating the first device die therein. A bottom surface of the first device die is coplanar with a bottom surface of the first encapsulating material. First dielectric layers are underlying the first device die. First redistribution lines are in the first dielectric layers and electrically coupling to the first device die. Second dielectric layers are overlying the first device die. Second redistribution lines are in the second dielectric layers and electrically coupling to the first redistribution lines. A second device die is overlying and electrically coupling to the second redistribution lines. No solder region connects the second device die to the second redistribution lines. A second encapsulating material encapsulates the second device die therein. A third device die is electrically coupled to the second redistribution lines. A third encapsulating material encapsulates the third device die therein.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su
  • Publication number: 20200294955
    Abstract: A package structure includes a first die, at least one second die, a semiconductor substrate and a glue layer. The semiconductor substrate includes no active devices. The glue layer is disposed between the at least one second die and the semiconductor substrate. The glue layer has a top surface adhered to the least one second die and a bottom surface adhered to a topmost surface of the semiconductor substrate. A total area of the bottom surface of the glue layer is substantially equal to a total area of the topmost surface of the semiconductor substrate, and a total thickness of the first die is substantially equal to only a total thickness of the at least one second die, the semiconductor substrate and the glue layer.
    Type: Application
    Filed: May 29, 2020
    Publication date: September 17, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hsien Huang, An-Jhih Su, Hsien-Wei Chen
  • Patent number: 10777430
    Abstract: A method includes placing an electronic die and a photonic die over a carrier, with a back surface of the electronic die and a front surface of the photonic die facing the carrier. The method further includes encapsulating the electronic die and the photonic die in an encapsulant, planarizing the encapsulant until an electrical connector of the electronic die and a conductive feature of the photonic die are revealed, and forming redistribution lines over the encapsulant. The redistribution lines electrically connect the electronic die to the photonic die. An optical coupler is attached to the photonic die. An optical fiber attached to the optical coupler is configured to optically couple to the photonic die.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: September 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Wei-Yu Chen
  • Publication number: 20200279833
    Abstract: A semiconductor device and method that utilize a surface device are provided. In an embodiment a fuse line comprises an underbump metallization which has two separate, electrically isolated parts. The two parts are bridged by an external connector, such as a solder ball in order to electrically connect the surface device. When, after testing, the surface device is determined to be defective, the fuse line may be disconnected by removing the external connector from the two separate parts, electrically isolating the surface device. In another embodiment the surface is located beneath a package within an integrated fan out package or is part of a multi-fan out package.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Inventors: Hsien-Wei Chen, Ying-Ju Chen, An-Jhih Su, Jie Chen
  • Patent number: 10756037
    Abstract: A package structure including a semiconductor die, an insulating encapsulant, a redistribution layer and a plurality of conductive terminals is provided. The semiconductor die includes a semiconductor substrate, a plurality of conductive pads and a plurality of conductive strips. The conductive pads are disposed on and connected to the plurality of conductive pads, wherein each of the conductive strips is physically connected to at least two conductive pads. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the insulating encapsulant and the semiconductor die, wherein the redistribution layer is electrically connected to the plurality of conductive strips. The plurality of conductive terminals is disposed on the redistribution layer.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hsien Huang, An-Jhih Su, Der-Chyang Yeh, Hua-Wei Tseng, Yueh-Ting Lin, Ming-Shih Yeh
  • Publication number: 20200258760
    Abstract: A semiconductor device includes a first die extending through a molding compound layer, a first dummy die having a bottom embedded in the molding compound layer, wherein a height of the first die is greater than a height of the first dummy die, and an interconnect structure over the molding compound layer, wherein a first metal feature of the interconnect structure is electrically connected to the first die and a second metal feature of the interconnect structure is over the first dummy die and extends over a sidewall of the first dummy die.
    Type: Application
    Filed: April 28, 2020
    Publication date: August 13, 2020
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Hsien-Wei Chen, Wei-Yu Chen
  • Patent number: 10741490
    Abstract: Device, package structure and method of forming the same are disclosed. The device includes a die encapsulated by an encapsulant, a conductive structure aside the die, and a dielectric layer overlying the conductive structure. The conductive structure includes a through via in the encapsulant, a redistribution line layer overlying the through via, and a seed layer overlying the redistribution line layer. The dielectric layer includes an opening, wherein the opening exposes a surface of the conductive structure, the opening has a scallop sidewall, and an included angle between a bottom surface of the dielectric layer and a sidewall of the opening is larger than about 60 degrees.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Wei Chen, An-Jhih Su, Li-Hsien Huang
  • Publication number: 20200251380
    Abstract: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.
    Type: Application
    Filed: April 20, 2020
    Publication date: August 6, 2020
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Jing-Cheng Lin, Hung-Jui Kuo
  • Publication number: 20200251456
    Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.
    Type: Application
    Filed: April 23, 2020
    Publication date: August 6, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Li-Hsien Huang, Po-Hao Tsai, Ming-Shih Yeh, Ta-Wei Liu
  • Patent number: 10734357
    Abstract: A chip package structure is provided. The chip package structure includes a first chip, a second chip, and a third chip. The second chip is between the first chip and the third chip. The chip package structure includes a first molding layer surrounding the first chip. The chip package structure includes a second molding layer surrounding the second chip. The chip package structure includes an insulating layer between the first molding layer and the second molding layer and between the first chip and the second chip. A side wall of the first molding layer, a side wall of the second molding layer, and a side wall of the insulating layer are substantially coplanar. The chip package structure includes a third molding layer surrounding the third chip, the first molding layer, the second molding layer, and the insulating layer.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yu Chen, Li-Hsien Huang, An-Jhih Su, Hsien-Wei Chen
  • Publication number: 20200243442
    Abstract: A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.
    Type: Application
    Filed: April 13, 2020
    Publication date: July 30, 2020
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Wen-Chih Chiou, Tsang-Jiuh Wu, Der-Chyang Yeh, Ming Shih Yeh
  • Patent number: 10720409
    Abstract: In some embodiments, a device includes a thermal-electrical-mechanical (TEM) chip having a functional circuit, a first die attached to a first side of the TEM chip, and a first via on the first side of the TEM chip and adjacent to the first die, the first via being electrically coupled to the TEM chip. The device also includes a first molding layer surrounding the TEM chip, the first die and the first via, where an upper surface of the first die and an upper surface of the first via are level with an upper surface of the first molding layer. The device further includes a first redistribution layer over the upper surface of the first molding layer and electrically coupled to the first via and the first die.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Der-Chyang Yeh, Hsien-Wei Chen, Li-Hsien Huang, Yueh-Ting Lin, Wei-Yu Chen, An-Jhih Su