Patents by Inventor An-Jhih Su

An-Jhih Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220137095
    Abstract: A board-like connector, a dual-ring bridge of a board-like connector, and a wafer testing assembly are provided. The board-like connector includes a plurality of dual-ring bridges spaced apart from each other and an insulating layer. Each of the dual-ring bridges includes two carrying rings, two cantilevers respectively extending from and being coplanar with the two carrying rings, two abutting columns respectively extending from the two cantilevers along two opposite directions, and a bridging segment that connects the two carrying rings. The insulating layer connects the two carrying rings of the dual-ring bridges, and the two abutting columns of the dual-ring bridges respectively protrude from two opposite sides of the insulating layer. The two abutting columns of each of the dual-ring bridges are configured to be respectively abutted against two boards.
    Type: Application
    Filed: September 24, 2021
    Publication date: May 5, 2022
    Inventors: KAI-CHIEH HSIEH, CHAO-CHIANG LIU, MENG-CHIEH CHENG, WEI-JHIH SU
  • Publication number: 20220137124
    Abstract: A board-like connector, a single-arm bridge of a board-like connector, and a wafer testing assembly are provided. The board-like connector includes a plurality of single-arm bridges spaced apart from each other and an insulating layer. Each of the single-arm bridges includes a carrier, a cantilever extending from and being coplanar with the carrier, an abutting column, and an abutting end portion, the latter two of which extend from the cantilever and are respectively arranged at two opposite sides of the cantilever. The insulating layer connects the carriers of the single-arm bridges, and the abutting column of each of the single-arm bridges protrudes from the insulating layer. The abutting column and the abutting end portion of each of the single-arm bridges are configured to abut against two boards, respectively.
    Type: Application
    Filed: September 24, 2021
    Publication date: May 5, 2022
    Inventors: KAI-CHIEH HSIEH, CHAO-CHIANG LIU, MENG-CHIEH CHENG, WEI-JHIH SU
  • Publication number: 20220140515
    Abstract: A board-like connector, a dual-arm bridge of a board-like connector, and a wafer testing assembly are provided. The board-like connector includes a plurality of dual-arm bridges spaced apart from each other and an insulating layer. Each of the dual-arm bridges includes a carrier, a first cantilever, a second cantilever, a first abutting column, and a second abutting column, the latter two of which extend from the first and second cantilevers along two opposite directions. The first cantilever and the second cantilever extend from and are coplanar with the carrier. The insulating layer connects the carriers of the dual-arm bridges. The first abutting column and second abutting column of each of the dual-arm bridges respectively protrude from two opposite sides of the insulating layer, and are configured to abut against two boards, respectively.
    Type: Application
    Filed: September 27, 2021
    Publication date: May 5, 2022
    Inventors: KAI-CHIEH HSIEH, CHAO-CHIANG LIU, MENG-CHIEH CHENG, WEI-JHIH SU
  • Publication number: 20220122952
    Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.
    Type: Application
    Filed: January 3, 2022
    Publication date: April 21, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Li-Hsien Huang, Po-Hao Tsai, Ming-Shih Yeh, Ta-Wei Liu
  • Patent number: 11276656
    Abstract: Semiconductor devices and methods of forming are provided. A molding compound extends along sidewalls of a first die and a second die. A redistribution layer is formed over the first die, the second die, and the molding compound. The redistribution layer includes a conductor overlying a gap between the first die and the second die. The conductor is routed at a first angle over an edge of the first die. The first angle is measured with respect to a straight line that extends along a shortest between the first die and the second die, and the first angle is greater than 0.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: March 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, An-Jhih Su, Tsung-Shu Lin
  • Publication number: 20220068880
    Abstract: The semiconductor structure includes a plurality of first dies, a plurality of second dies disposed over each of the first dies, and a dielectric material surrounding the plurality of first dies and the plurality of second die. Each of the second dies overlaps a portion of each first die.
    Type: Application
    Filed: November 12, 2021
    Publication date: March 3, 2022
    Inventors: CHEN-HUA YU, CHI-HSI WU, DER-CHYANG YEH, HSIEN-WEI CHEN, AN-JHIH SU, TIEN-CHUNG YANG
  • Patent number: 11264363
    Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure including a dielectric structure, a redistribution line, and a seal ring structure. The redistribution line and the seal ring structure are in the dielectric structure, the seal ring structure continuously surrounds the redistribution line, the seal ring structure includes a first seal ring and a second seal ring over and electrically connected to the first seal ring, and the redistribution structure has a first sidewall, a first surface, and a second surface opposite to the first surface. The chip package structure includes a chip structure over the first surface. The chip package structure includes a ground bump over the second surface. The chip package structure includes a conductive shielding film covering the chip structure and the first sidewall of the redistribution structure.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, An-Jhih Su, Jing-Cheng Lin, Po-Hao Tsai
  • Patent number: 11251071
    Abstract: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Jing-Cheng Lin, Hung-Jui Kuo
  • Publication number: 20220018876
    Abstract: A probe card device and a fence-like probe thereof are provided. The fence-like probe includes a stroke segment, a fan-out segment, and a testing segment. The stroke segment is in an elongated shape defining a longitudinal direction, and the stroke segment has two end portions and a plurality of penetrating slots that are arranged along a fan-out direction perpendicular to the longitudinal direction, so that the stroke segment is deformable to store an elastic force by being applied with a force. The fan-out segment and the testing segment are respectively connected to the two end portions of the stroke segment. The fan-out segment has a fixing point arranged away from the stroke segment, and the testing segment has an abutting point arranged away from the stroke segment. Along the fan-out direction, the fixing point is spaced apart from the abutting point by a fan-out distance.
    Type: Application
    Filed: September 15, 2020
    Publication date: January 20, 2022
    Inventors: WEN-TSUNG LEE, Hsun-Tai Wei, KAI-CHIEH HSIEH, WEI-JHIH SU
  • Patent number: 11226354
    Abstract: A probe card device and a fence-like probe thereof are provided. The fence-like probe includes a stroke segment, a fan-out segment, and a testing segment. The stroke segment is in an elongated shape defining a longitudinal direction, and the stroke segment has two end portions and a plurality of penetrating slots that are arranged along a fan-out direction perpendicular to the longitudinal direction, so that the stroke segment is deformable to store an elastic force by being applied with a force. The fan-out segment and the testing segment are respectively connected to the two end portions of the stroke segment. The fan-out segment has a fixing point arranged away from the stroke segment, and the testing segment has an abutting point arranged away from the stroke segment. Along the fan-out direction, the fixing point is spaced apart from the abutting point by a fan-out distance.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: January 18, 2022
    Assignee: CHUNGHWA PRECISION TEST TECH. CO., LTD.
    Inventors: Wen-Tsung Lee, Hsun-Tai Wei, Kai-Chieh Hsieh, Wei-Jhih Su
  • Publication number: 20220013461
    Abstract: A semiconductor device includes a bridge and a plurality of dies. The bridge is free of active devices and includes a substrate, an interconnect structure, a redistribution layer structure and a plurality of conductive connectors. The interconnect structure includes at least one dielectric layer and a plurality of first conductive features in the at least one dielectric layer. The redistribution layer structure includes at least one polymer layer and a plurality of second conductive features in the at least one polymer layer, wherein a sidewall of the interconnect structure is substantially flush with a sidewall of the redistribution layer structure. The conductive connectors are electrically connected to one another by the redistribution layer structure and the interconnect structure. The bridge electrically connects the plurality of dies.
    Type: Application
    Filed: July 9, 2020
    Publication date: January 13, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hung Lin, An-Jhih Su, Der-Chyang Yeh, Shih-Guo Shen, Chia-Nan Yuan, Ming-Shih Yeh
  • Publication number: 20220011346
    Abstract: A probe card device and a fan-out probe thereof are provided. The fan-out probe includes a stroke segment, a fan-out segment, and a testing segment. The stroke segment is in a straight shape defining a longitudinal direction, and the stroke segment has two end portions. The stroke segment is bendable when the two end portions are respectively applied with forces along two opposite directions. The fan-out segment and the testing segment are respectively connected to the two end portions of the stroke segment. The fan-out segment has a fixing point arranged away from the stroke segment, and the testing segment has an abutting point arranged away from the stroke segment. Along a fan-out direction perpendicular to the longitudinal direction, the fixing point is spaced apart from the abutting point by a fan-out distance.
    Type: Application
    Filed: September 14, 2020
    Publication date: January 13, 2022
    Inventors: WEN-TSUNG LEE, Hsun-Tai Wei, KAI-CHIEH HSIEH, WEI-JHIH SU
  • Patent number: 11217570
    Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Li-Hsien Huang, Po-Hao Tsai, Ming-Shih Yeh, Ta-Wei Liu
  • Patent number: 11209461
    Abstract: A probe card device and a neck-like probe thereof are provided. The neck-like probe includes a conductive pin and a ring-shaped insulator. The conductive pin includes a stroke segment and two end segments extending from the stroke segment. The stroke segment has two broad side surfaces and two narrow side surfaces, and each of the broad side surfaces has a long slot extending from one of the narrow side surfaces to the other one. The two long slots have a minimum distance therebetween that is 75%-95% of a maximum distance between the two broad side surfaces. The ring-shaped insulator surrounds a portion of the conductive pin having the two long slots, and a portion of the neck-like probe corresponding in position to a part of the ring-shaped insulator on the two broad side surfaces has a thickness that is 85%-115% of the maximum distance.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: December 28, 2021
    Assignee: CHUNGHWA PRECISION TEST TECH. CO., LTD.
    Inventors: Wen-Tsung Lee, Hsun-Tai Wei, Kai-Chieh Hsieh, Wei-Jhih Su
  • Patent number: 11204371
    Abstract: A probe card device and a directivity probe thereof are provided. The directivity probe having an elongated shape includes a conductive pin and a ring-shaped insulator. The conductive pin includes a stroke segment and two end segments respectively extending from the stroke segment. The stroke segment has two broad side surfaces and two narrow side surfaces, and has only one transverse slot that is recessed in one of the two broad side surfaces and that extends from one of the two narrow side surfaces to the other narrow side surface. The transverse groove has a maximum depth that is 1%-10% of a maximum distance between the two broad side surfaces. The stroke segment of the directivity probe can be bent by applying a force to the two end segments, and an inflection point of the bent stroke segment is located in the transverse slot.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: December 21, 2021
    Assignee: CHUNGHWA PRECISION TEST TECH. CO., LTD.
    Inventors: Wen-Tsung Lee, Hsun-Tai Wei, Kai-Chieh Hsieh, Wei-Jhih Su
  • Publication number: 20210375842
    Abstract: Various packages and methods of forming packages are discussed. According to an embodiment, a package includes a processor die at least laterally encapsulated by an encapsulant, a memory die at least laterally encapsulated by the encapsulant, and a redistribution structure on the encapsulant. The processor die is communicatively coupled to the memory die through the redistribution structure. According to further embodiments, the memory die can include memory that is a cache of the processor die, and the memory die can comprise dynamic random access memory (DRAM).
    Type: Application
    Filed: August 16, 2021
    Publication date: December 2, 2021
    Inventors: Chen-Hua Yu, Der-Chyang Yeh, An-Jhih Su
  • Publication number: 20210358854
    Abstract: A redistribution structure for a semiconductor device and a method of forming the same are provided. The semiconductor device includes a die encapsulated by an encapsulant, the die including a pad, and a connector electrically connected to the pad. The semiconductor device further includes a first via in physical contact with the connector. The first via is laterally offset from the connector by a first non-zero distance in a first direction. The first via has a tapered sidewall.
    Type: Application
    Filed: September 9, 2020
    Publication date: November 18, 2021
    Inventors: Chen-Hua Yu, An-Jhih Su, Der-Chyang Yeh, Li-Hsien Huang, Ming Shih Yeh
  • Patent number: 11177238
    Abstract: A semiconductor structure includes a plurality of first dies, a second die disposed over each of the first dies, and a dielectric material surrounding the first dies and the second die. The second dies overlaps a portion of each of the first dies. A dimension of the second die is different from a dimension of the first dies.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: November 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Hua Yu, Chi-Hsi Wu, Der-Chyang Yeh, Hsien-Wei Chen, An-Jhih Su, Tien-Chung Yang
  • Patent number: 11175312
    Abstract: A staggered probe card and a conductive probe are provided. The staggered probe card includes an upper guide board, a lower guide board spaced apart from the upper guide board, and a plurality of conductive probes arranged in rows and passing through the upper and lower guide boards. Each of the conductive probes has an elongated structure defining a longitudinal direction, and includes a bottom surface and two long side surfaces respectively connected to two edges of the bottom surface. A distance between the two long side surfaces gradually decreases in a tapering direction that extends away from the bottom surface. In two of the rows of the conductive probes adjacent to each other, any two long side surfaces respectively belonging to the two adjacent rows and arranged adjacent to each other have a lateral interval along a direction that is non-parallel to the arrangement direction.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: November 16, 2021
    Assignee: CHUNGHWA PRECISION TEST TECH. CO., LTD.
    Inventors: Kai-Chieh Hsieh, Hsiao-Kang Li, Ying-Ming Tiao, Wei-Jhih Su
  • Patent number: 11177142
    Abstract: A method includes attaching a first die and a second die to a carrier; forming a molding material between the first die and second die; and forming a redistribution structure over the first die, the second die and the molding material, the redistribution structure includes a first redistribution region; a second redistribution region; and a dicing region between the first redistribution region and the second redistribution region. The method further includes forming a first opening and a second opening in the dicing region, the first opening and the second opening extending through the redistribution structure and exposing the molding material; and separating the first die and the second die by cutting through a portion of the molding material aligned with the dicing region from a second side of the molding material toward the first side of the molding material, the second side opposing the first side.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Hsien Huang, Yueh-Ting Lin, An-Jhih Su, Ming Shih Yeh, Der-Chyang Yeh