Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

Abstract: A semiconductor structure includes a first semiconductor package, a second semiconductor package, a heat spreader and an dielectric layer. The first semiconductor package includes a plurality of first semiconductor chips and a first dielectric encapsulation layer disposed around the plurality of the first semiconductor chips. The second semiconductor package is disposed over and corresponds to one of the plurality of first semiconductor chips, wherein the second semiconductor package includes a plurality of second semiconductor chips and a second dielectric encapsulation layer disposed around the plurality of second semiconductor chips. The heat spreader is disposed over and corresponds to another of the plurality of first semiconductor chips. The dielectric layer is disposed over the first semiconductor package and around the second semiconductor package and the heat spreader.

Abstract: A cantilever probe card device and a focusing probe thereof are provided. The focusing probe includes a soldering segment, a testing segment, two outer elastic arms spaced apart from each other, and a focusing portion. The testing segment is spaced apart from the soldering segment along an arrangement direction, and has a needle tip, an outer edge, and an inner edge that is opposite to the outer edge. Each of the two outer elastic arms has two end portions respectively connected to the soldering segment and the inner edge of the testing segment. The focusing portion is connected to the inner edge and is located between the needle tip and the two outer elastic arms, and has a plurality of focusing points arranged on one side thereof away from the two outer elastic arms.

Abstract: A cantilever probe card device and an elastic probe thereof are provided. The elastic probe includes a soldering segment, a testing segment, two outer elastic arms spaced apart from each other. The testing segment is spaced apart from the soldering segment along an arrangement direction, and has a needle tip, an outer edge, and an inner edge that is opposite to the outer edge. Each of the two outer elastic arms has two end portions respectively connected to the soldering segment and the inner edge of the testing segment. Moreover, one of the two outer elastic arms adjacent to the needle tip is defined as a first outer elastic arm, and another one of the two outer elastic arms is defined as a second outer elastic arm. Specifically, a length of the first outer elastic arm is greater than a length of the second outer elastic arm.

Abstract: A cantilever probe card and a probe module thereof are provided. The probe module includes a supporting board, a substrate disposed on the supporting board, a plurality of cantilever probes, and a plurality of fine adjustment members. The substrate has a non-planar shape and has a difference of warpage along a testing direction. One end of each of the cantilever probes is connected to the substrate, and another end of each of the cantilever probes is a free end. The fine adjustment members are spaced apart from each other and are disposed between the supporting board and the substrate. Each of the fine adjustment members is configured to be independently operable along the testing direction for changing a distance between the supporting board and the substrate. The substrate is deformable through at least one of the fine adjustment members so as to reduce the difference of warpage.

Abstract: A cantilever probe card and a carrier thereof are provided. The carrier includes a seat, a metal sheet, and a plurality of coarse adjustment members. The metal sheet is assembled to the seat and has a carrying surface. The coarse adjustment members are spaced apart from each other and are disposed between the seat and the metal sheet. Each of the coarse adjustment members is configured to be independently operable along a testing direction for changing a distance between the carrying surface and the seat. The carrying surface has a plurality of assembling regions spaced apart from each other, and at least two of the assembling regions have an assembling tolerance therebetween along the testing direction. The metal sheet of the carrier is deformable through at least one of the coarse adjustment members so as to reduce the assembling tolerance along the testing direction.

Abstract: In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.

Abstract: A vertical probe card having different probes is provided, and includes a first guiding board unit, a second guiding board unit, and a plurality of fence-like probes passing through the first and the second guiding board units. Each of the fence-like probes has a probe length within a range from 5 mm to 8 mm, and includes a fence-like segment, a connection segment, and a testing segment. The fence-like segment includes a penetrating slot having a length greater than 65% of the probe length. The fence-like segment includes two arms respectively arranged at two opposite sides of the penetrating slot and spaced apart from each other by an adjustment distance within a range from 10 ?m to 120 ?m. The fence-like probes include a first probe and a second probe, which have a same contact force and are configured to respectively meet different electrical transmission requirements.

Abstract: A vertical probe card and a fence-like probe thereof are provided. The fence-like probe has a probe length within a range from 5 mm to 8 mm. The fence-like probe includes a fence-like segment, a ceramic layer, a connection segment, and a testing segment. The fence-like segment has an elongated shape defining a longitudinal direction, and the fence-like segment has a penetrating slot that is formed along the longitudinal direction and that has a length greater than 65% of the probe length. The ceramic layer is directly formed on an outer surface of the fence-like segment and covers two long walls of the penetrating slot. The connection segment and the testing segment are respectively connected to two end portions of the fence-like segment, and is not formed on the connection segment and the testing segment.

Abstract: A vertical probe card device and a fence-like probe thereof are provided. The fence-like probe has a probe length within a range from 5 mm to 8 mm. The fence-like probe includes a fence-like segment, a connection segment, and a testing segment. The fence-like segment has an elongated shape defining a longitudinal direction, and the fence-like segment has a penetrating slot and a first protrusion. The penetrating slot is formed along the longitudinal direction and has a length greater than 65% of the probe length. The first protrusion extends from one of two long walls of the penetrating slot by a first predetermined width and is spaced apart from another one of the two long walls of the penetrating slot by a first gap. The connection segment and the testing segment are respectively connected to two end portions of the fence-like segment.

Abstract: A modular vertical probe card having different probes is provided, and includes a first guiding board unit, a second guiding board unit, and a plurality of conductive probes that pass through the first and the second guiding board units. The conductive probes have a same probe length. Each of the conductive probes includes a stroke segment located between the first guiding board unit and the second guiding board unit, a connection segment, and a testing segment, the latter two of which are respectively connected to two ends of the stroke segment. The stroke segments of the conductive probes have N number of shapes different from each other to allow the conductive probes to have a same contact force and to be configured to meet N number of electrical transmission requirements different from each other, in which N is a positive integer greater than one.

Abstract: A chip package structure is provided. The chip package structure includes a first chip, a second chip, and a third chip. The chip package structure includes a first molding layer surrounding the first chip and the second chip. The first molding layer is a single layer structure. A first boundary surface between the passivation layer and the second molding layer extends toward the first chip. The chip package structure includes a second molding layer surrounding the third chip and the first molding layer. A first bottom surface of the first molding layer and a second bottom surface of the second molding layer are substantially coplanar.

Abstract: A board-like connector, a single-arm bridge of a board-like connector, and a wafer testing assembly are provided. The board-like connector includes a plurality of single-arm bridges spaced apart from each other and an insulating layer. Each of the single-arm bridges includes a carrier, a cantilever extending from and being coplanar with the carrier, an abutting column, and an abutting end portion, the latter two of which extend from the cantilever and are respectively arranged at two opposite sides of the cantilever. The insulating layer connects the carriers of the single-arm bridges, and the abutting column of each of the single-arm bridges protrudes from the insulating layer. The abutting column and the abutting end portion of each of the single-arm bridges are configured to abut against two boards, respectively.

Abstract: A semiconductor structure includes a first semiconductor package, a second semiconductor package, a heat spreader and an underfill layer. The first semiconductor package includes a plurality of lower semiconductor chips and a first dielectric encapsulation layer disposed around the plurality of the lower semiconductor chips. The second semiconductor package is disposed over and corresponds to one of the plurality of lower semiconductor chips, wherein the second semiconductor package includes a plurality of upper semiconductor chips and a second dielectric encapsulation layer disposed around the plurality of upper semiconductor chips. The heat spreader is disposed over and corresponds to another of the plurality of lower semiconductor chips. The underfill layer is disposed over the first semiconductor package and around the second semiconductor package and the heat spreader.

Abstract: In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.

Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.

Abstract: A semiconductor device includes a first die extending through a molding compound layer, a first dummy die having a bottom embedded in the molding compound layer, wherein a height of the first die is greater than a height of the first dummy die, and an interconnect structure over the molding compound layer, wherein a first metal feature of the interconnect structure is electrically connected to the first die and a second metal feature of the interconnect structure is over the first dummy die and extends over a sidewall of the first dummy die.

Abstract: Various packages and methods of forming packages are discussed. According to an embodiment, a package includes a processor die at least laterally encapsulated by an encapsulant, a memory die at least laterally encapsulated by the encapsulant, and a redistribution structure on the encapsulant. The processor die is communicatively coupled to the memory die through the redistribution structure. According to further embodiments, the memory die can include memory that is a cache of the processor die, and the memory die can comprise dynamic random access memory (DRAM).

Abstract: A board-like connector, a dual-arm bridge of a board-like connector, and a wafer testing assembly are provided. The board-like connector includes a plurality of dual-arm bridges spaced apart from each other and an insulating layer. Each of the dual-arm bridges includes a carrier, a first cantilever, a second cantilever, a first abutting column, and a second abutting column, the latter two of which extend from the first and second cantilevers along two opposite directions. The first cantilever and the second cantilever extend from and are coplanar with the carrier. The insulating layer connects the carriers of the dual-arm bridges. The first abutting column and second abutting column of each of the dual-arm bridges respectively protrude from two opposite sides of the insulating layer, and are configured to abut against two boards, respectively.

Abstract: A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.