Abstract: A spread spectrum digital communication receiver, of the type comprising an input memory buffer (16) for storing samples of an input signal (y(k)) and a code generator circuit (30) for generating a re-generated user code, incorporates a device (24) for the estimation of a channel delay profile comprises: a basic correlator (32) having a first input (41) for sequentially reading from a memory location of the input memory buffer (16) a plurality of samples of the input signal (y(k)), a second input (43) for receiving from the code generator circuit (30) a re-generated user code, and an output terminal for generating, by means of a correlation operation between the plurality of samples of the input signal and the regenerated user code, a first value of the channel delay profile energy (DP(1)); and a memory controller circuit (36) for addressing said the memory buffer (16) so that the first input (41) of the basic correlator (32) is successively fed with the content of several memory locations of the memory buffe

Abstract: A device for maintaining fine alignment between an incoming spread spectrum signal and a locally generated code in a digital communication receiver comprises: a delay line for storing a plurality of consecutive samples (E-1, E, M, L, L+1) of the incoming spread spectrum signal; three digitally controlled interpolators for determining by interpolation between consecutive samples an interpolated early sample, an interpolated middle sample, and an interpolated late sample; two correlators for calculating an error signal as the difference between the energy of the symbols computed from the interpolated early and late samples; a circuit for generating a control signal for controlling the interpolation phase of the digitally controlled interpolator for the early sample, and a digital non-linear filter, for smoothing the control signal of the interpolator for the early sample, enabling the update operation of the control signal only when the absolute value of the error signal at a time instant n is smaller than the

Abstract: A method for the synchronization of a digital telecommunication receiver comprises the steps of:—storing a plurality of consecutive samples E?1, E, M, L, L+1 of an incoming spread spectrum signal in a delay line 56;—determining by interpolation between consecutive samples of the incoming spread spectrum signal, by means of a first digitally controlled interpolator 26, an interpolated early sample (e) anticipating an optimal sampling time instant;—determining by interpolation between consecutive samples of the incoming spread spectrum signal, by means of a second digitally controlled interpolator 24, an interpolated middle sample (m) corresponding to the optimal sampling time instant;—determining by interpolation between consecutive samples of the incoming spread spectrum signal, by means of a third digitally controlled interpolator 28, an interpolated late sample (l) delayed with respect to the optimal sampling time instant;—calculating an error signal ? as the difference between the energy of the symbols com

Abstract: A method for the estimation of the transfer function of a transmission channel in a receiving system of UMTS type envisages the computation of a plurality of channel coefficients, included among known channel coefficients corresponding to pilot symbols, through the reiteration of an interpolation algorithm, capable of calculating an intermediate point (Z, f(Z)) between a first extreme and a second extreme of a determined interval, the first extreme being formed by at least two known points and the second extreme being formed by at least one known point, the intermediate point to be calculated having as abscissa (Z) the abscissa value of the mean point between the points defining the interval rounded off to the integer closest to the first extreme, and having as ordinate (F(Z)) the arithmetic average between the ordinate of the known point of the second extreme and the ordinate of a point, chosen between the two known points of the first extreme, having a distance from the intermediate point equal to the dista

Abstract: A device for maintaining fine alignment between an incoming spread spectrum signal and a locally generated code in a digital communication receiver comprises:—delay line (56) for storing a plurality of consecutive samples (E?1, E, M, L, L+1) of the incoming spread spectrum signal;—three digitally controlled interpolators (24, 26, 28) for determining by interpolation between consecutive samples an interpolated early sample (e), an interpolated middle sample (m) and an interpolated late sample (1);—two correlators (30, 32) for calculating an error signal (?) as the difference between the energy of the symbols computed from the interpolated early (e) and late (1) samples;—a circuit for generating a control signal (SOUT?) for controlling the interpolation phase of the digitally controlled interpolator (24) for the early sample (e), and—a digital non-linear filter (68), for smoothing the control signal (SOUT?) of the interpolator (24) for the early sample (e), enabling the update operation of the control signal on

Abstract: A spread spectrum digital communication receiver, of the type comprising an input memory buffer (16) for storing samples of an input signal (y(k)) and a code generator circuit (30) for generating a re-generated user code, incorporates a device (24) for the estimation of a channel delay profile comprises: a basic correlator (32) having a first input (41) for sequentially reading from a memory location of the input memory buffer (16) a plurality of samples of the input signal (y(k)), a second input (43) for receiving from the code generator circuit (30) a re-generated user code, and an output terminal for generating, by means of a correlation operation between the plurality of samples of the input signal and the regenerated user code, a first value of the channel delay profile energy (DP(1)); and a memory controller circuit (36) for addressing said the memory buffer (16) so that the first input (41) of the basic correlator (32) is successively fed with the content of several memory locations of the memory buffe

Abstract: A method for the synchronization of a digital telecommunication receiver comprises the steps of:—storing a plurality of consecutive samples E?1, B, M, 1, L+1 of an incoming spread spectrum signal in a delay line 56;—determining by interpolation between consecutive samples of the incoming spread spectrum signal, by means of a first digitally controlled interpolator 26, an interpolated early sample (e) anticipating an optimal sampling time instant;—determining by interpolation between consecutive samples of the incoming spread spectrum signal, by means of a second digitally controlled interpolator 24, an interpolated middle sample (m) corresponding to the optimal sampling time instant;—determining by interpolation between consecutive samples of the incoming spread spectrum signal, by means of a third digitally controlled interpolator 28, an interpolated late sample (1) delayed with respect to the optimal sampling time instant;—calculating an error signal ? as the difference between the energy of the symbols com

Abstract: A method for the estimation of the transfer function of a transmission channel in a receiving system of UMTS type envisages the computation of a plurality of channel coefficients, included among known channel coefficients corresponding to pilot symbols, through the reiteration of an interpolation algorithm, capable of calculating an intermediate point (Z, f(Z)) between a first extreme and a second extreme of a determined interval, the first extreme being formed by at least two known points and the second extreme being formed by at least one known point, the intermediate point to be calculated having as abscissa (Z) the abscissa value of the mean point between the points defining the interval rounded off to the integer closest to the first extreme, and having as ordinate (F(Z)) the arithmetic average between the ordinate of the known point of the second extreme and the ordinate of a point, chosen between the two known points of the first extreme, having a distance from the intermediate point equal to the dista

Abstract: The circuit for motion estimation in digitised video sequence encoders comprises at least an integrated circuit component (IM, IM1 . . . IMn) which is arranged to perform either the function of determining motion vectors and associated costs for different prediction modes, or the function of vector refinement, possibly in addition to prediction mode selection. The circuit (IM) is based on the use of two operating units (M1, M2) which are arranged to concurrently process in different ways different pixel groups according to a MIMD technique. Preferably, when the circuit performs motion vector determination, the operating units (M1, M2) are programmed to execute a genetic algorithm exploiting an initial vector population taking into account the temporal and spatial correlations in the picture.

Abstract: An integrated circuit for manipulating digitized video sequences is provided, for use in a system for transmission and reception of compressed video sequences to perform, possibly with the aid of an external memory, reordering, format conversion, prediction and motion compensation on the pictures in a sequence. The device has memory for temporarily storing sequences to be manipulated and data read from the external memory; a circuit for decoding information about the manipulations to be performed; address circuitry for transferring the data between the device and the external memory; circuitry for configuring the device by means of a remote processing unit; circuitry for processing the data read from the external memory; and circuitry for arranging the output sequences in the format required by the function to be performed. A controller may control, supervise and set up the functions to be performed.

Abstract: A decoder for audio signals belonging to audio-visual streams coded in accordance with standard ISO/IEC 11172 is provided. The decoder has a presentation unit (UP) which is controlled by a first and a second clock signal, depending on the desired sampling rate, and is associated to device for (SAV) managing audio-video synchronization. The latter device starts the presentation of output data by comparing a first timing signal (SCR), representative of a system clock signal, and a second timing signal (PTS), representative of a correct instant of data presentation, independently generate the two clock signals (CLK24, CLK22) and corrects the signal corresponding to the desired sampling rate with the use of a feedback circuit which includes a digital filter (FD).

Abstract: A high speed digital signal transceiver in CMOS technology, in which the receiver has a clock signal extraction circuit, which is capable of self-aligning on incoming data with no spurious locks. Utilizing the PLL technique, the circuit generates a clock signal locked to the incoming signal utilizing a local oscillator, voltage-controlled by two feedback loops, a main one for frequency and phase corrections and a secondary one for phase correction. Moreover, original circuit solutions for the phase detectors and the low-pass filters are also envisaged.