Abstract: A system and method are disclosed in which a first non-volatile memory includes blocks that store data, and a second memory that stores error correction information related to the blocks storing the data. The first memory and the second memory are of different types.

Abstract: A method and system are disclosed in which a first non-volatile memory includes blocks that store data, and a second memory that stores overhead information related to the blocks storing the data. The amount of the second memory storing the overhead information related to the at least one block of the plurality of blocks is varied.

Abstract: A system and method are disclosed in which a first non-volatile memory includes blocks that store data, and a second memory that stores error correction information related to the blocks storing the data. The first memory and the second memory are of different types.

Abstract: The present disclosure includes methods and devices for determining sensing voltages. One such method includes comparing data associated with a number of template distributions to data associated with a first threshold voltage distribution and a second threshold voltage distribution associated with a number of memory cells programmed to particular adjacent program states, determining an intersection of the first and second threshold voltage distributions based on a template distribution of the number template distributions which most closely compares to the first and second threshold voltage distributions, and using the determined intersection to determine a sensing voltage used to sense the number of memory cells programmed to the particular adjacent program states.

Abstract: A method and system are disclosed in which a first non-volatile memory includes blocks that store data, and a second memory that stores overhead information related to the blocks storing the data. The amount of the second memory storing the overhead information related to the at least one block of the plurality of blocks is varied.

Abstract: The present disclosure includes methods and devices for determining sensing voltages. One such method includes comparing data associated with a number of template distributions to data associated with a first threshold voltage distribution and a second threshold voltage distribution associated with a number of memory cells programmed to particular adjacent program states, determining an intersection of the first and second threshold voltage distributions based on a template distribution of the number template distributions which most closely compares to the first and second threshold voltage distributions, and using the determined intersection to determine a sensing voltage used to sense the number of memory cells programmed to the particular adjacent program states.

Abstract: Embodiments for providing improved reliability or extended life for a non-volatile memory component may comprise a secondary non-volatile memory component to store error correction information, for example.

Abstract: The present disclosure includes methods and devices for determining sensing voltages. One such method includes comparing data associated with a number of template distributions to data associated with a first threshold voltage distribution and a second threshold voltage distribution associated with a number of memory cells programmed to particular adjacent program states, determining an intersection of the first and second threshold voltage distributions based on a template distribution of the number template distributions which most closely compares to the first and second threshold voltage distributions, and using the determined intersection to determine a sensing voltage used to sense the number of memory cells programmed to the particular adjacent program states.

Abstract: A nonvolatile memory device includes a memory block including a plurality of memory cells grouped by word lines, an operation circuit group configured to perform a program operation or a read operation for the memory cells, and a control circuit configured to control the operation circuit group to set each of threshold voltages of a group of the memory cells, coupled to a word line selected from the word lines, to one of an erase level and five program levels in response to input data.

Abstract: A MOS capacitor comprises a semiconductor substrate, a first well region of a first conductivity type formed in the substrate, at least one doped region formed in the first well region, and an insulated gate layer insulatively disposed over a surface of the first well region. The at least one doped region and the insulated gate layer respectively form a first and a second electrode of the capacitor. The first well region is electrically connected to the at least one doped region to be at a same electrical potential of the first terminal of the capacitor.

Abstract: A MOS capacitor comprises a semiconductor substrate, a first well region of a first conductivity type formed in the substrate, at least one doped region formed in the first well region, and an insulated gate layer insulatively disposed over a surface of the first well region. The at least one doped region and the insulated gate layer respectively form a first and a second electrode of the capacitor. The first well region is electrically connected to the at least one doped region to be at a same electrical potential of the first terminal of the capacitor.

Abstract: An integrated electronic device having a first charge pump, intended to drive a first line having a high capacitive load, and a second charge pump having a high current pumping capacity and intended to drive a second line, a controlled switch is interposed between the outputs of the two pumps, such as to connect the output of the high current capacity pump to the first line, to charge the first line quickly to the preset voltage, without the first charge pump being oversized. When the voltage present on the first line becomes greater than the voltage at the output of the second charge pump, owing to the current required by the second line, the switch is opened. A common phase generator which drives both the pumps is also provided.

Abstract: Circuit for discharging to ground, supplied by a supply voltage, comprising a reference voltage, a negative potential node, first circuitry adapted to couple the negative potential node to the reference voltage in response to a control signal. Second circuitry is provided adapted to determine in the first circuitry the passage of a controlled current for the discharge of the negative potential node.

Abstract: The present invention relates to an output stage for an electronic memory device and for low supply-voltage applications and is the type comprising a final stage of the pull-up/pull-down type made up of a complementary pair of transistors inserted between a primary reference supply voltage and a secondary reference voltage and a voltage regulator for the control terminals of said transistors. The regulator is a voltage booster using at least one bootstrap capacitor to increase the current flowing in the final stage by boosting the voltage applied to said control terminals.

Abstract: An electronic circuit generates a stable voltage signal for the polarization during a reading step of a UPROM redundancy cell incorporating at least one memory element of EPROM or Flash type, having at least one terminal to be polarized, and MOS transistors which connect such memory element to a low voltage power supply reference. The circuit includes a current mirror structure with a first control branch and a second output branch. The current mirror stricture includes a first series of MOS transistors (M2, M3, M4) in said first branch between the supply reference and a ground; and a second series of transistors (M5, M6, M7) in said second branch. The circuit also includes an input terminal connected to the gate terminal of a transistor of the first series of transistors and an output terminal corresponding to an interconnection node of the second series of transistors. The stable voltage is obtained through a current which passes through at least a pair of transistors of the second series.

Abstract: A temperature-related voltage generating circuit has an input terminal receiving a control voltage independent of temperature, and an output terminal delivering a temperature-related control voltage. The input and output terminals are connected together through at least an amplifier stage adapted to set an output reference voltage from a comparison of input voltages. The voltage generating circuit also includes a generator element generating a varying voltage with temperature and connected between a ground voltage reference and a non-inverting input terminal of the amplifier stage. The amplifier stage has an output terminal adapted to deliver a multiple of the varying voltage with temperature to an inverting input terminal of a comparator stage.

Abstract: A charge pump comprises at least one charge pump stage including a first diode having an anode and a cathode, and a capacitor having a first plate connected to the cathode of the diode and a second plate connected to a clock signal that periodically varies between a reference voltage and a supply voltage, the anode of said diode forming a first terminal of the charge pump. The charge pump further comprises a second diode having an anode connected to the cathode of the first diode and a cathode forming a second terminal of the charge pump, first switching means for selectively coupling the first terminal of the charge pump to the voltage supply and second switching means for selectively coupling the second terminal of the charge pump to the reference voltage.

Abstract: A charge pump circuit for integrated memory devices includes a plurality of stages cascade connected between an input terminal having a first voltage reference and an output terminal. Each stage includes a boost capacitor and one PMOS transistor functioning as a pass transistor. Each PMOS transistor has conduction terminals connected between the previous stage and the next stage, and a control terminal receiving a drive signal. The pass transistors are driven with a voltage that has a ground value when they are to be turned on, and a voltage equal to the highest of the positive voltages involved when they are to be turned off. The highest of the positive voltages involved is the output from the charge pump.

Abstract: A negative charge pump circuit comprises a plurality of charge pump stages connected in series to each other. Each stage has a stage input terminal and a stage output terminal. A first stage has the stage input terminal connected to a reference voltage, a final stage has the stage output terminal operatively connected to an output terminal of the charge pump at which a negative voltage is developed; intermediate stages have the respective stage input terminal connected to the stage output terminal of a preceding stage and the respective stage output terminal connected to the stage input terminal of a following stage.

Abstract: A circuit device programs non-volatile memory cells having a single voltage supply, wherein each cell comprises a floating gate transistor having source and drain terminals and a control gate terminal, with the drain terminal being supplied a program voltage from a voltage booster circuit. The device includes a means of supplying a constant drain current to the drain terminal of the memory cell; an element for sampling the drain current drawn through the cell; and a means of voltage feedback driving the control gate terminal of the cell according to the sampled value of the drain current.