Abstract: A three-dimensional transistor includes a semiconductor substrate, a fin coupled to the substrate, the fin including an active region across a top portion thereof, the active region including a source, a drain and a channel region therebetween. The transistor further includes a gate situated above the channel region, and a gate contact situated in the active region, no portion thereof being electrically coupled to the source or drain. The transistor is achieved by removing a portion of the source/drain contact situated beneath the gate contact during fabrication.

Abstract: The invention relates to novel polyethylene glycol (PEG) based prodrug of Adrenomedullin, to processes for preparation thereof, to the use thereof for treatment and/or prevention of diseases, and to the use thereof for producing medicaments for treatment and/or prevention of diseases, especially of cardiovascular, edematous and/or inflammatory disorders.

Abstract: A method of forming SRB finFET fins first with a cut mask that is perpendicular to the subsequent fin direction and then with a cut mask that is parallel to the fin direction and the resulting device are provided. Embodiments include forming a SiGe SRB on a substrate; forming a Si layer over the SRB; forming an NFET channel and a SiGe PFET channel in the Si layer; forming cuts through the NFET and PFET channels, respectively, and the SRB down to the substrate, the cuts formed on opposite ends of the substrate and perpendicular to the NFET and PFET channels; forming fins in the SRB and the NFET and PFET channels, the fins formed perpendicular to the cuts; forming a cut between the NFET and PFET channels, the cut formed parallel to the fins; filling the cut with oxide; and recessing the oxide down to the SRB.

Abstract: The invention relates to novel polyethylene glycol (PEG) based prodrug of Adrenomedullin, to processes for preparation thereof, to the use thereof for treatment and/or prevention of diseases, and to the use thereof for producing medicaments for treatment and/or prevention of diseases, especially of cardiovascular, edematous and/or inflammatory disorders.

Abstract: The present application relates to novel aryl- and hetaryl-substituted imidazo[1,2-a]pyridine-3-carboxamides, to processes for preparation thereof, to the use thereof, alone or in combinations, for treatment and/or prophylaxis of diseases, and to the use thereof for production of medicaments for treatment and/or prophylaxis of diseases, especially for treatment and/or prophylaxis of cardiovascular disorders.

Abstract: One method disclosed herein includes, among other things, forming a gate contact opening in a layer of insulating material, wherein the gate contact opening is positioned at least partially vertically above a active region, the gate contact opening exposing a portion of at least a gate cap layer of a gate structure, performing at least one etching process to remove the gate cap layer and recess a sidewall spacer so as to thereby define a spacer cavity and expose at least an upper surface of a gate electrode within the gate contact opening, filling the spacer cavity with an insulating material while leaving the upper surface of the gate electrode exposed, and forming a conductive gate contact in the gate contact opening.

Abstract: One illustrative method disclosed herein includes removing the sidewall spacers and a gate cap layer so as to thereby expose an upper surface and sidewalls of a sacrificial gate structure, forming an etch stop layer above source/drain regions of a device and on the sidewalls and upper surface of the sacrificial gate structure, forming a first layer of insulating material above the etch stop layer, removing the sacrificial gate structure so as to define a replacement gate cavity that is laterally defined by portions of the etch stop layer, forming a replacement gate structure in the replacement gate cavity, and forming a second gate cap layer above the replacement gate structure.

Abstract: The invention relates to novel substituted bipiperidinyl derivatives, to processes for their preparation, to their use for the treatment and/or prevention of diseases and to their use for preparing medicaments for the treatment and/or prevention of diseases, in particular for the treatment and/or prevention of diabetic microangiopathies, diabetic ulcers on the extremities, in particular for promoting wound healing of diabetic foot ulcers, diabetic heart failure, diabetic coronary microvascular heart disorders, peripheral and cardiac vascular disorders, thromboembolic disorders and ischaemias, peripheral circulatory disturbances, Raynaud's phenomenon, CREST syndrome, microcirculatory disturbances, intermittent claudication, and peripheral and autonomous neuropathies.

Abstract: The present application relates to novel substituted piperidinyltetrahydroquinolines, to processes for their preparation, to their use for the treatment and/or prevention of diseases and to their use for preparing medicaments for the treatment and/or prevention of diseases, in particular for the treatment and/or prevention of diabetic microangiopathies, diabetic ulcers on the extremities, in particular for promoting wound healing of diabetic foot ulcers, diabetic heart failure, diabetic coronary microvascular heart disorders, peripheral and cardial vascular disorders, thromboembolic disorders and ischaemias, peripheral circulatory disturbances, Raynaud's phenomenon, CREST syndrome, microcirculatory disturbances, intermittent claudication, and peripheral and autonomous neuropathies.

Abstract: The present application relates to novel substituted piperidinyltetrahydroquinolines, to processes for their preparation, to their use for the treatment and/or prevention of diseases and to their use for preparing medicaments for the treatment and/or prevention of diseases, in particular for the treatment and/or prevention of diabetic microangiopathies, diabetic ulcers on the extremities, in particular for promoting wound healing of diabetic foot ulcers, diabetic heart failure, diabetic coronary microvascular heart disorders, peripheral and cardial vascular disorders, thromboembolic disorders and ischaemias, peripheral circulatory disturbances, Raynaud's phenomenon, CREST syndrome, microcirculatory disturbances, intermittent claudication, and peripheral and autonomous neuropathies.

Abstract: One example of a novel integrated circuit product disclosed herein includes, among other things, a lateral FinFET device comprising a first gate structure having a first upper surface positioned above a semiconductor substrate and a vertical FinFET device comprising a second gate structure having a second upper surface positioned above the semiconductor substrate, wherein the first upper surface of the first gate structure is positioned at a first height level above a reference surface of the semiconductor substrate and the second upper surface of the second gate structure is positioned at a second height level above the reference surface of the semiconductor substrate, the first height level being greater than the second height level.

Abstract: The present application relates to novel 3-phenylpropionic acid derivatives which carry a branched or cyclic alkyl substituent in the 3-position, to processes for their preparation, to their use for the treatment and/or prevention of diseases and to their use for preparing medicaments for the treatment and/or prevention of diseases, in particular for the treatment and/or prevention of cardiovascular diseases.

Abstract: One example of a novel integrated circuit product disclosed herein includes, among other things, a lateral FinFET device comprising a first gate structure having a first upper surface positioned above a semiconductor substrate and a vertical FinFET device comprising a second gate structure having a second upper surface positioned above the semiconductor substrate, wherein the first upper surface of the first gate structure is positioned at a first height level above a reference surface of the semiconductor substrate and the second upper surface of the second gate structure is positioned at a second height level above the reference surface of the semiconductor substrate, the first height level being greater than the second height level.

Abstract: Methods and interconnect structures for circuit structure transistors are provided. The methods include, for instance: providing one or more fins above a substrate, and an insulating material over the fin(s) and the substrate; providing barrier structures extending into the insulating material, the barrier structures being disposed along opposing sides of the fin(s); exposing a portion of the fin(s) and the barrier structures; and forming an interconnect structure extending over the fin(s), the barrier structures confining the interconnect structure to a defined dimension transverse to the fin(s). Exposing the portion of the fin(s) and barrier structures may include isotropically etching the insulating material with an etchant that selectively etches the insulating material without affecting a barrier material of the barrier structures.

Abstract: A non-planar semiconductor structure includes a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate and surrounded at a lower portion thereof by a layer of isolation material, gate structure(s) and confined epitaxial material above active regions of the raised structures, the confined epitaxial material having recessed portion(s) therein. Dummy gate structures surrounding a portion of each of the raised structures are initially used, and the confined epitaxial material is created before replacing the dummy gate structures with final gate structures. The structure further includes silicide on upper surfaces of a top portion of the confined epitaxial material, and contacts above the silicide, the contacts including separate contacts electrically coupled to only one area of confined epitaxial material and common contact(s) electrically coupling two adjacent areas of the confined epitaxial material.

Abstract: A non-planar semiconductor structure includes a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate and surrounded at a lower portion thereof by a layer of isolation material, gate structure(s) and confined epitaxial material above active regions of the raised structures, the confined epitaxial material having recessed portion(s) therein. Dummy gate structures surrounding a portion of each of the raised structures are initially used, and the confined epitaxial material is created before replacing the dummy gate structures with final gate structures. The structure further includes silicide on upper surfaces of a top portion of the confined epitaxial material, and contacts above the silicide, the contacts including separate contacts electrically coupled to only one area of confined epitaxial material and common contact(s) electrically coupling two adjacent areas of the confined epitaxial material.

Abstract: The present application relates to novel substituted 5-fluoro-1H-pyrazolopyridines, to processes for their preparation, to their use alone or in combinations for the treatment and/or prophylaxis of diseases, and to their use for producing medicaments for the treatment and/or prophylaxis of diseases, in particular for the treatment and/or prophylaxis of cardiovascular disorders.

Abstract: Methods for converting planar designs to FinFET designs in the design and fabrication of integrated circuits are provided. In one embodiment, a method for converting a planar integrated circuit design to a non-planar integrated circuit design includes identifying a rectangular silicon active area in the planar integrated circuit design, superimposing a FinFET design grid comprising a plurality of equidistantly-spaced parallel grid lines over the rectangular silicon active area such that two sides of the rectangular silicon active area are parallel to the grid lines, and generating a rectangular active silicon marker area encompassing the silicon active area. Furthermore, the method includes generating fin mandrels longitudinally along every other grid line of the plurality of grid lines and within the active silicon marker area and the silicon active area, and removing the fin mandrels from areas of the design grid outside of the active silicon marker area.

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin that is positioned above and vertically spaced apart from an upper surface of a semiconductor substrate, the fin having an upper surface, a lower surface and first and second side surfaces, wherein an axis of the fin in a height direction of the fin is oriented substantially parallel to the upper surface of the substrate, and wherein a first side surface of the fin contacts a first insulating material, forming a gate structure around the upper surface, the second side surface and the lower surface of the fin, and forming a gate contact structure that is conductively coupled to the gate structure.

Abstract: One illustrative method disclosed herein includes forming a plurality of initial fins in a substrate, wherein at least one of the initial fins is a to-be-removed fin, forming a material adjacent the initial fins, forming a fin removal masking layer above the plurality of initial fins, removing a desired portion of the at least one to-be-removed fin by: (a) performing a recess etching process on the material to remove a portion, but not all, of the material positioned adjacent the sidewalls of the at least one to-be-removed fin, (b) after performing the recess etching process, performing a fin recess etching process to remove a portion, but not all, of the at least one to be removed fin and (c) repeating steps (a) and (b) until the desired amount of the at least one to-be-removed fin is removed.