Patents by Inventor Andrei Warkentin

Andrei Warkentin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190391814
    Abstract: An example method of implementing firmware runtime services in a computer system having a processor with a plurality of hierarchical privilege levels, the method including: calling, from software executing at a first privilege level of the processor, a runtime service stub in a firmware of the computer system; executing, by the runtime service stub, an upcall instruction from the first privilege level to a second privilege level of the processor that is more privileged than the first privilege level; and executing, by a handler, a runtime service at the second privilege level in response to execution of the upcall instruction.
    Type: Application
    Filed: June 20, 2018
    Publication date: December 26, 2019
    Inventors: Andrei WARKENTIN, Cyprien LAPLACE, Alexander FAINKICHEN, Ye LI, Regis DUCHESNE
  • Patent number: 10489258
    Abstract: Negative path testing in a bootloader environment can include backing up a global state of a component under test, injecting a fault to trigger an error in the component under test in a bootloader environment, executing error handling instructions until a checkpoint of the component under test in the bootloader environment is reached, restoring the global state to the component under test from the backup, and restarting the component under test.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: November 26, 2019
    Assignee: Vmware, Inc.
    Inventors: Daniel Muller, Andrei Warkentin
  • Publication number: 20190286558
    Abstract: A computer system provides a mechanism for assuring a safe, non-preemptible access to a private data area (PRDA) belonging to a CPU. PRDA accesses generally include obtaining an address of a PRDA and performing operations on the PRDA using the obtained address. Safe, non-preemptible access to a PRDA generally ensures that a context accesses the PRDA of the CPU on which the context is executing, but not the PRDA of another CPU. While a context executes on a first CPU, the context obtains the address of the PRDA. After the context is migrated to a second CPU, the context performs one or more operations on the PRDA belonging to the second CPU using the address obtained while the context executed on the first CPU. In another embodiment, preemption and possible migration of a context from one CPU to another CPU is delayed while a context executes non-preemptible code.
    Type: Application
    Filed: May 23, 2019
    Publication date: September 19, 2019
    Inventors: Cyprien LAPLACE, Harvey TUCH, Andrei WARKENTIN, Adrian DRZEWIECKI
  • Publication number: 20190258590
    Abstract: An example method of accessing a computing system includes: providing serial terminal driver configured to interface a serial port in a hardware platform of the computer system; providing a console object configured to communicate with an operating system (OS) in a software platform of the computer system and the serial terminal driver; connecting to the console object through the serial port via a computer terminal; sending text and commands from the console object to the computer terminal; and rendering, by the computer terminal, a console for presentation on a display of the computer terminal.
    Type: Application
    Filed: February 19, 2018
    Publication date: August 22, 2019
    Inventors: Andrei WARKENTIN, Cyprien LAPLACE, Ye LI, Alexander FAINKICHEN, Regis DUCHESNE
  • Patent number: 10379870
    Abstract: A method of initializing a secondary processor pursuant to a soft reboot of system software comprises storing code to be executed by the secondary processor in memory, building first page tables to map the code into a first address space and second page tables to identically map the code into a second address space, fetching a first instruction of the code based on a first virtual address in the first address space and the first page tables, and executing the code beginning with the first instruction to switch from the first to the second page tables. The method further comprises, fetching a next instruction of the code using a second virtual address, which is identically mapped to a corresponding machine address, turning off a memory management unit of the secondary processor, and executing a waiting loop until a predetermined location in the physical memory changes in value.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: August 13, 2019
    Assignee: VMware, Inc.
    Inventors: Andrei Warkentin, Cyprien Laplace, Regis Duchesne, Alexander Fainkichen, Ye Li
  • Publication number: 20190227934
    Abstract: An example method of maintaining cache coherency in a virtualized computing system includes: trapping access to a memory page by guest software in a virtual machine at a hypervisor managing the virtual machine, where the memory page is not mapped in a second stage page table managed by the hypervisor; performing cache coherency maintenance for instruction and data caches of a central processing unit (CPU) in the virtualized computing system in response to the trap; mapping the memory page in the second stage page table with execute permission; and resuming execution of the virtual machine.
    Type: Application
    Filed: January 23, 2018
    Publication date: July 25, 2019
    Inventors: Ye LI, Cyprien LAPLACE, Andrei WARKENTIN, Alexander FAINKICHEN, Regis DUCHESNE
  • Publication number: 20190213033
    Abstract: Techniques for optimizing CPU usage in a host system based on VM guest OS power and performance management are provided. In one embodiment, a hypervisor of the host system can capture information from a VM guest OS that pertains to a target power or performance state set by the guest OS for a vCPU of the VM. The hypervisor can then perform, based on the captured information, one or more actions that align usage of host CPU resources by the vCPU with the target power or performance state.
    Type: Application
    Filed: March 15, 2019
    Publication date: July 11, 2019
    Inventors: Andrei Warkentin, Cyprien Laplace, Regis Duchesne, Ye Li, Alexander Fainkichen
  • Publication number: 20190213095
    Abstract: A method of detecting virtualization in a computing system, which includes a processor having at least three hierarchical privilege levels including a third privilege level more privileged than a second privilege level, the second privilege level more privileged than a first privilege level, is described. The method includes: executing a program on the processor at a privilege level less privileged than the third privilege level, the program including a load-exclusive instruction of the processor, followed by at least one instruction of the processor capable of being trapped to the third privilege level, followed by a store-exclusive instruction of the processor; and determining presence or absence of virtualization software at least a portion of which executes at the third privilege level in response to a return status of the store-exclusive instruction.
    Type: Application
    Filed: January 9, 2018
    Publication date: July 11, 2019
    Inventors: Andrei WARKENTIN, Cyprien LAPLACE, Regis DUCHESNE, Ye LI, Alexander FAINKICHEN
  • Patent number: 10331556
    Abstract: A computer system provides a mechanism for assuring a safe, non-preemptible access to a private data area (PRDA) belonging to a CPU. PRDA accesses generally include obtaining an address of a PRDA and performing operations on the PRDA using the obtained address. Safe, non-preemptible access to a PRDA generally ensures that a context accesses the PRDA of the CPU on which the context is executing, but not the PRDA of another CPU. While a context executes on a first CPU, the context obtains the address of the PRDA. After the context is migrated to a second CPU, the context performs one or more operations on the PRDA belonging to the second CPU using the address obtained while the context executed on the first CPU. In another embodiment, preemption and possible migration of a context from one CPU to another CPU is delayed while a context executes non-preemptible code.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: June 25, 2019
    Assignee: VMware, INC.
    Inventors: Cyprien Laplace, Harvey Tuch, Andrei Warkentin, Adrian Drzewiecki
  • Publication number: 20190179646
    Abstract: Examples provide for automatically provisioning hosts in a cloud environment. A cloud daemon generates a cloud host-state configuration, for a given cloud instance of a host, stored on a cloud metadata service prior to first boot of the given cloud instance of the host. A first boot of a plurality of cloud instances of hosts is performed using a stateless, master boot image lacking host-specific configuration data. On completion of the first boot of a given cloud instance of a host, the cloud host-state configuration is installed on the master boot image to generate a self-configured boot image including host-specific configuration data for the given cloud instance of the host. A second boot is performed on the given cloud instance of the host by executing the self-configured boot image to automatically provision the given cloud instance of the host in the cloud environment.
    Type: Application
    Filed: October 2, 2018
    Publication date: June 13, 2019
    Inventors: Andrei Warkentin, Harvey Tuch, William Lam
  • Patent number: 10282226
    Abstract: Techniques for optimizing CPU usage in a host system based on VM guest OS power and performance management are provided. In one embodiment, a hypervisor of the host system can capture information from a VM guest OS that pertains to a target power or performance state set by the guest OS for a vCPU of the VM. The hypervisor can then perform, based on the captured information, one or more actions that align usage of host CPU resources by the vCPU with the target power or performance state.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: May 7, 2019
    Assignee: VMWARE, INC.
    Inventors: Andrei Warkentin, Cyprien Laplace, Regis Duchesne, Ye Li, Alexander Fainkichen
  • Patent number: 10261800
    Abstract: Techniques for recovering virtual machine state and boot information used to boot an installed guest operating system on systems where the information has either been lost or is not present are described.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: April 16, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Andrei Warkentin, Jacob Oshins
  • Patent number: 10255090
    Abstract: In a virtualized computer system operable in more than two hierarchical privilege levels, components of a hypervisor, which include a virtual machine kernel and virtual machine monitors (VMMs), are assigned to different privilege levels. The virtual machine kernel operates at a low privilege level to be able to exploit certain features provided by the low privilege level, and the VMMs operate at a high privilege level to support execution of virtual machines. Upon determining that a context switch from the virtual machine kernel to a VMM is to be performed, the computer system exits the low privilege level, and enters the high privilege level to execute a trampoline that supports context switches to VMMs, such as state changes, and then the VMM. The trampoline is deactivated after execution control is switched to the VMM.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: April 9, 2019
    Assignee: VMware, Inc.
    Inventors: Harvey Tuch, Andrei Warkentin
  • Publication number: 20190065213
    Abstract: An example method of provisioning a virtual appliance to a virtualized computing system, comprising: deploying the virtual appliance to the virtualized computing system, the virtual appliance including a system partition, one or more disk images, and configuration data, the configuration data defining a virtual machine executable on each of a plurality of processor architectures, the system partition configured to boot on any one of the plurality of processor architectures; and booting the virtual appliance from the system partition.
    Type: Application
    Filed: January 26, 2018
    Publication date: February 28, 2019
    Inventors: Ye LI, Cyprien LAPLACE, Andrei WARKENTIN, Alexander FAINKICHEN, Regis DUCHESNE
  • Publication number: 20190026118
    Abstract: A method of providing software support of an input/output (TO) device of a computing system having an advanced configuration and power interface (ACPI) subsystem executing therein is described. The method includes: processing an ACPI namespace to determine first and second identifiers of the IO device; determining absence of a device driver for the IO device based on the first identifier; and loading a first fallback device driver portion based on the second identifier, the first fallback device driver portion providing an interface to a control method in the ACPI namespace, the control method executable by the ACPI subsystem to implement a second fallback device driver portion that supports at least a portion of functionality for the IO device.
    Type: Application
    Filed: July 19, 2017
    Publication date: January 24, 2019
    Inventors: Andrei WARKENTIN, Cyprien LAPLACE
  • Publication number: 20190026232
    Abstract: An example method of scanning a guest virtual address (GVA) space generated by a guest operating system executing in a virtual machine of a virtualized computing system includes setting, in a scan of the GVA space by a hypervisor that manages the virtual machine, a current GVA to a first GVA in the GVA space; executing, on a processor allocated to the virtual machine, an address translation instruction, which is in an instruction set of the processor, to perform a first address translation of the current GVA; reading a register of the processor to determine a first error resulting from the first address translation; determining, in response to the first error, a level of a faulting page table in a first page table hierarchy generated by the guest operating system; and setting the current GVA to a second GVA based on the level of the faulting page table.
    Type: Application
    Filed: July 20, 2017
    Publication date: January 24, 2019
    Inventors: Andrei WARKENTIN, Alexander FAINKICHEN, Cyprien LAPLACE, Ye LI, Regis DUCHESNE
  • Publication number: 20190026203
    Abstract: Negative path testing in a bootloader environment can include backing up a global state of a component under test, injecting a fault to trigger an error in the component under test in a bootloader environment, executing error handling instructions until a checkpoint of the component under test in the bootloader environment is reached, restoring the global state to the component under test from the backup, and restarting the component under test.
    Type: Application
    Filed: July 18, 2017
    Publication date: January 24, 2019
    Applicant: VMware, Inc.
    Inventors: Daniel Muller, Andrei Warkentin
  • Patent number: 10185571
    Abstract: A method of re-mapping memory regions for firmware run-time services to a virtual address space of a kernel executed on a processor, includes the steps of selecting a re-mapping policy for re-mapping the memory regions for the firmware run-time services, creating a new mapping according to the selected re-mapping policy, and making a call to an application programming interface exposed by the firmware to apply the new map and re-map the memory regions for the firmware to the virtual address space of the kernel.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: January 22, 2019
    Assignee: VMWARE, INC.
    Inventors: Andrei Warkentin, Timothy P. Mann, Alexander Fainkichen
  • Patent number: 10185664
    Abstract: A method of re-mapping a boot loader image from a first to a second address space includes: determining a difference in a virtual address of the boot loader image in the first and second address spaces; building page tables for a third address space that maps a code section within the boot loader image at first and second address ranges separated by the difference and the code section causes execution to jump from a first instruction in the first address range to a second instruction in the second address range; executing an instruction of the code section in the first address space using pages tables for the first address space; executing the first instruction and then the second instruction using the page tables for the third address space; and executing an instruction of the boot loader image in the second address space using page tables for the second address space.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: January 22, 2019
    Assignee: VMware, Inc.
    Inventors: Andrei Warkentin, Cyprien Laplace, Regis Duchesne, Alexander Fainkichen, Ye Li
  • Publication number: 20190012179
    Abstract: A method of initializing a secondary processor pursuant to a soft reboot of system software comprises storing code to be executed by the secondary processor in memory, building first page tables to map the code into a first address space and second page tables to identically map the code into a second address space, fetching a first instruction of the code based on a first virtual address in the first address space and the first page tables, and executing the code beginning with the first instruction to switch from the first to the second page tables. The method further comprises, fetching a next instruction of the code using a second virtual address, which is identically mapped to a corresponding machine address, turning off a memory management unit of the secondary processor, and executing a waiting loop until a predetermined location in the physical memory changes in value.
    Type: Application
    Filed: July 7, 2017
    Publication date: January 10, 2019
    Inventors: Andrei WARKENTIN, Cyprien LAPLACE, Regis DUCHESNE, Alexander FAINKICHEN, Ye LI