Patents by Inventor Andrew D. Bailey, III

Andrew D. Bailey, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170062290
    Abstract: Systems and methods for processing a semiconductor wafer includes a plasma processing chamber. The plasma processing chamber includes an exterior, an interior region with a wafer receiving mechanism and a viewport disposed on a sidewall of the plasma processing chamber providing visual access from the exterior to the wafer received on the wafer receiving mechanism. A camera is mounted to the viewport of the plasma processing chamber on the exterior and coupled to an image processor. The image processor includes pattern recognition logic to match images of emerging pattern captured and transmitted by the camera, to a reference pattern and to generate signal defining an endpoint when a match is detected. A system process controller coupled to the image processor and the plasma processing chamber receives the signal from the image processor and adjusts controls of one or more resources to stop the etching operation.
    Type: Application
    Filed: November 16, 2016
    Publication date: March 2, 2017
    Inventors: Alan Jeffrey Miller, Evelio Sevillano, Jorge Luque, Andrew D. Bailey, III, Qing Xu
  • Patent number: 9564308
    Abstract: The embodiments provide apparatus and methods for removal of etch byproducts, dielectric films and metal films near the substrate bevel edge, and chamber interior to avoid the accumulation of polymer byproduct and deposited films and to improve process yield. In an exemplary embodiment, a plasma processing chamber configured to clean a bevel edge of a substrate is provided. The plasma processing chamber includes a substrate support configured to receive the substrate. The plasma processing chamber also includes a bottom edge electrode surrounding the substrate support. The bottom edge electrode and the substrate support are electrically isolated from one another by a bottom dielectric ring. A surface of the bottom edge electrode facing the substrate is covered by a bottom thin dielectric layer. The plasma processing chamber further includes a top edge electrode surrounding a top insulator plate opposing the substrate support. The top edge electrode is electrically grounded.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: February 7, 2017
    Assignee: Lam Research Corporation
    Inventors: Gregory S. Sexton, Andrew D. Bailey, III, Andras Kuthi, Yunsang Kim
  • Patent number: 9548189
    Abstract: A substrate etching system includes an etching control module, a filtering module, and an endpoint module. The etching control module selectively begins plasma etching of a substrate within an etching chamber. The filtering module, during the plasma etching of the substrate: receives a signal including endpoint information; decomposes the signal using empirical mode decomposition (EMD); and generates a filtered signal based on results of the EMD. The endpoint module indicates when an endpoint of the plasma etching of the substrate has been reached based on the filtered signal. The etching control module ends the plasma etching of the substrate in response to the indication that the endpoint of the plasma etching of the substrate has been reached.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: January 17, 2017
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Luc Albarede, Yassine Kabouzi, Jorge Luque, Andrew D. Bailey, III
  • Patent number: 9543225
    Abstract: Systems and methods for processing a semiconductor wafer includes a plasma processing chamber. The plasma processing chamber includes an exterior, an interior region with a wafer receiving mechanism and a viewport disposed on a sidewall of the plasma processing chamber providing visual access from the exterior to the wafer received on the wafer receiving mechanism. A camera is mounted to the viewport of the plasma processing chamber on the exterior and coupled to an image processor. The image processor includes pattern recognition logic to match images of emerging pattern captured and transmitted by the camera, to a reference pattern and to generate signal defining an endpoint when a match is detected. A system process controller coupled to the image processor and the plasma processing chamber receives the signal from the image processor and adjusts controls of one or more resources to stop the etching operation.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: January 10, 2017
    Assignee: Lam Research Corporation
    Inventors: Alan Jeffrey Miller, Evelio Sevillano, Jorge Luque, Andrew D Bailey, III, Qing Xu
  • Publication number: 20160370796
    Abstract: A system for controlling a condition of a wafer processing chamber is disclosed. According the principles of the present disclosure, the system includes memory and a first controller. The memory stores a plurality of profiles of respective ones of a plurality of first control elements. The plurality of first control elements are arranged throughout the chamber. The first controller determines non-uniformities in a substrate processing parameter associated with the plurality of first control elements. The substrate processing parameter is different than the condition of the chamber. The first controller adjusts at least one of the plurality of profiles based on the non-uniformities in the substrate processing parameter and a sensitivity of the substrate processing parameter to the condition.
    Type: Application
    Filed: September 21, 2015
    Publication date: December 22, 2016
    Inventors: Marcus Musselman, Juan Valdivia, III, Hua Xiang, Andrew D. Bailey, III, Yoko Yamaguchi, Qian Fu, Aaron Eppler
  • Publication number: 20160370795
    Abstract: A system including a controller, an interface, and a calibration controller. The controller is configured to (i) select a set of fields, and (ii) based on the set of fields, supply control effort to first actuators in zones of a chamber. The interface is configured to receive feedback signals from sensors. The feedback signals are indicative of fields respectively of the zones. The controller is configured to adjust an amount of control effort supplied to the actuators based on the fields. The calibration controller is configured to, based on the fields, generate calibration values for each of the sensors. The calibration values for each of the sensors are indicative of field contributions corresponding respectively to the actuators.
    Type: Application
    Filed: September 21, 2015
    Publication date: December 22, 2016
    Inventors: Marcus Musselman, Andrew D. Bailey, III
  • Publication number: 20160370788
    Abstract: A system includes memory that stores compensation information that associates process setpoint temperatures with respective adjustment values. The respective adjustment values include a first adjustment value corresponding to a first temperature compensation scheme and at least one second adjustment value corresponding to a second compensation scheme. A temperature compensation module receives a first process setpoint temperature, retrieves the compensation information from the memory based on the received first process setpoint temperature, calculates a first compensated temperature based on the received first process setpoint temperature, the first adjustment value, and the second adjustment value, and controls a temperature of a component of a substrate processing system according to the first compensated temperature.
    Type: Application
    Filed: September 23, 2015
    Publication date: December 22, 2016
    Inventors: Andrew D. Bailey, III, Marcus Carbery
  • Publication number: 20160358784
    Abstract: Methods for etching a substrate in a plasma processing chamber having at least a primary plasma generating region and a secondary plasma generating region separated from said primary plasma generating region by a semi-barrier structure. The method includes generating a primary plasma from a primary feed gas in the primary plasma generating region. The method also includes generating a secondary plasma from a secondary feed gas in the secondary plasma generating region to enable at least some species from the secondary plasma to migrate into the primary plasma generating region. The method additionally includes etching the substrate with the primary plasma after the primary plasma has been augmented with migrated species from the secondary plasma.
    Type: Application
    Filed: August 15, 2016
    Publication date: December 8, 2016
    Inventors: Eric A. Hudson, Andrew D. Bailey, III, Rajinder Dhindsa
  • Publication number: 20160314943
    Abstract: A substrate etching system includes an etching control module, a filtering module, and an endpoint module. The etching control module selectively begins plasma etching of a substrate within an etching chamber. The filtering module, during the plasma etching of the substrate: receives a signal including endpoint information; decomposes the signal using empirical mode decomposition (EMD); and generates a filtered signal based on results of the EMD. The endpoint module indicates when an endpoint of the plasma etching of the substrate has been reached based on the filtered signal. The etching control module ends the plasma etching of the substrate in response to the indication that the endpoint of the plasma etching of the substrate has been reached.
    Type: Application
    Filed: April 23, 2015
    Publication date: October 27, 2016
    Inventors: Luc Albarede, Yassine Kabouzi, Jorge Luque, Andrew D. Bailey, III
  • Patent number: 9418859
    Abstract: Methods for etching a substrate in a plasma processing chamber having at least a primary plasma generating region and a secondary plasma generating region separated from said primary plasma generating region by a semi-barrier structure. The method includes generating a primary plasma from a primary feed gas in the primary plasma generating region. The method also includes generating a secondary plasma from a secondary feed gas in the secondary plasma generating region to enable at least some species from the secondary plasma to migrate into the primary plasma generating region. The method additionally includes etching the substrate with the primary plasma after the primary plasma has been augmented with migrated species from the secondary plasma.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: August 16, 2016
    Assignee: Lam Research Corporation
    Inventors: Eric A. Hudson, Andrew D. Bailey, III, Rajinder Dhindsa
  • Publication number: 20160148786
    Abstract: Embodiments for processing a substrate in a pulsed plasma chamber are provided. A processing apparatus with two chambers, separated by a plate fluidly connecting the chambers, includes a continuous wave (CW) controller, a pulse controller, and a system controller. The CW controller sets the voltage and the frequency for a first radio frequency (RF) power source coupled to a top electrode. The pulse controller is operable to set voltage, frequency, ON-period duration, and OFF-period duration for a pulsed RF signal generated by a second RF power source coupled to the bottom electrode. The system controller is operable to set parameters to regulate the flow of species between the chambers to assist in the negative-ion etching, to neutralize excessive positive charge on the wafer surface during afterglow in the OFF period, and to assist in the re-striking of the bottom plasma during the ON period.
    Type: Application
    Filed: January 29, 2016
    Publication date: May 26, 2016
    Inventors: Alexei Marakhtanov, Rajinder Dhindsa, Eric Hudson, Andrew D. Bailey, III
  • Publication number: 20160111309
    Abstract: An EFEM useful for transferring wafers to and from wafer processing modules comprises an enclosure having a controlled environment therein bounded by a front wall, a back wall, first and second side walls, a top wall, and a bottom wall. The first side wall and the second side wall include two or more wafer load ports wherein each wafer load port is adapted to receive a FOUP. The front wall includes wafer ports configured to attach to respective load locks operable to allow a wafer to be transferred to a front wall cluster processing tool. The back wall includes a wafer port adapted to be in operational relationship with a back wall cluster processing tool. A robot in the EFEM enclosure is operable to transfer wafers through the wafer load ports, the first front wall wafer port, the second front wall wafer port, and the back wall wafer port.
    Type: Application
    Filed: October 17, 2014
    Publication date: April 21, 2016
    Inventors: Thorsten Lill, Vahid Vahedi, Candi Kristoffersen, Andrew D. Bailey, III, Meihua Shen, Rangesh Raghavan, Gary Bultman
  • Publication number: 20160111261
    Abstract: A system and method of identifying a selected process point in a multi-mode pulsing process includes applying a multi-mode pulsing process to a selected wafer in a plasma process chamber, the multi-mode pulsing process including multiple cycles, each one of the cycles including at least one of multiple, different phases. At least one process output variable is collected for a selected at least one of the phases, during multiple cycles for the selected wafer. An envelope and/or a template of the collected at least one process output variable can be used to identify the selected process point. A first trajectory for the collected process output variable of a previous phase can be compared to a second trajectory of the process output variable of the selected phase. A multivariate analysis statistic of the second trajectory can be calculated and used to identify the selected process point.
    Type: Application
    Filed: October 24, 2014
    Publication date: April 21, 2016
    Inventors: Yassine Kabouzi, Jorge Luque, Andrew D. Bailey, III, Mehmet Derya Tetiker, Ramkumar Subramanian, Yoko Yamaguchi
  • Publication number: 20160079039
    Abstract: A semiconductor wafer processing apparatus includes a first electrode exposed to a first plasma generation volume, a second electrode exposed to a second plasma generation volume, and a gas distribution unit disposed between the first and second plasma generation volumes. The first electrode is defined to transmit radiofrequency (RF) power to the first plasma generation volume, and distribute a first plasma process gas to the first plasma generation volume. The second electrode is defined to transmit RF power to the second plasma generation volume, and hold a substrate in exposure to the second plasma generation volume. The gas distribution unit includes an arrangement of through-holes defined to fluidly connect the first plasma generation volume to the second plasma generation volume. The gas distribution unit also includes an arrangement of gas supply ports defined to distribute a second plasma process gas to the second plasma generation volume.
    Type: Application
    Filed: November 10, 2015
    Publication date: March 17, 2016
    Inventors: Rajinder Dhindsa, Alexei Marakhtanov, Andrew D. Bailey III
  • Patent number: 9281166
    Abstract: A process chamber includes a wafer support to mount a wafer to be processed in the process chamber, with the wafer having an annular edge exclusion area. A first electrically grounded ring extends in an annular path radially outward of the edge exclusion area and is electrically isolated from the wafer support. A second electrode is configured with a center area opposite to the wafer support. A second electrically grounded ring extends in an annular path radially outward of the second electrode and the edge exclusion area. The second electrically grounded ring is electrically isolated from the center area. An annular mount section has a DC bias ring, and the DC bias ring opposes the edge exclusion area when the wafer is present. A DC control circuit is provided for applying a DC voltage to the DC bias ring.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: March 8, 2016
    Assignee: Lam Research Corporation
    Inventors: Yunsang Kim, Andrew D. Bailey, III
  • Publication number: 20160064215
    Abstract: The embodiments provide apparatus and methods for removal of etch byproducts, dielectric films and metal films near the substrate bevel edge, and chamber interior to avoid the accumulation of polymer byproduct and deposited films and to improve process yield. In an exemplary embodiment, a plasma processing chamber configured to clean a bevel edge of a substrate is provided. The plasma processing chamber includes a substrate support configured to receive the substrate. The plasma processing chamber also includes a bottom edge electrode surrounding the substrate support. The bottom edge electrode and the substrate support are electrically isolated from one another by a bottom dielectric ring. A surface of the bottom edge electrode facing the substrate is covered by a bottom thin dielectric layer. The plasma processing chamber further includes a top edge electrode surrounding a top insulator plate opposing the substrate support. The top edge electrode is electrically grounded.
    Type: Application
    Filed: November 10, 2015
    Publication date: March 3, 2016
    Inventors: Gregory S. Sexton, Andrew D. Bailey III, Andras Kuthi, Yunsang Kim
  • Patent number: 9263240
    Abstract: A system and method of plasma processing includes a plasma chamber including a substrate support and an upper electrode opposite the substrate support, the upper electrode having a plurality of concentric temperature control zones and a controller coupled to the plasma chamber.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: February 16, 2016
    Assignee: Lam Research Corporation
    Inventors: Alexei Marakhtanov, Rajinder Dhindsa, Ryan Bise, Lumin Li, Sang Ki Nam, Jim Rogers, Eric Hudson, Gerardo Delgadino, Andrew D. Bailey, III, Mike Kellogg, Anthony de la Llera
  • Publication number: 20150357209
    Abstract: Apparatus, methods, and computer programs for semiconductor processing in a capacitively-coupled plasma chamber are provided. A chamber includes a bottom radio frequency (RF) signal generator, a top RF signal generator, and an RF phase controller. The bottom RF signal generator is coupled to the bottom electrode in the chamber, and the top RF signal generator is coupled to the top electrode. Further, the bottom RF signal is set at a first phase, and the top RF signal is set at a second phase. The RF phase controller is operable to receive the bottom RF signal and operable to set the value of the second phase. Additionally, the RF phase controller is operable to track the first phase and the second phase to maintain a time difference between the maximum of the top RF signal and the minimum of the bottom RF signal at approximately a predetermined constant value, resulting in an increase of the negative ion flux to the surface of the wafer.
    Type: Application
    Filed: August 14, 2015
    Publication date: December 10, 2015
    Inventors: Alexei Marakhtanov, Mirzafer K. Abatchev, Rajinder Dhindsa, Eric Hudson, Andrew D. Bailey, III
  • Patent number: 9184043
    Abstract: The embodiments provide apparatus and methods for removal of etch byproducts, dielectric films and metal films near the substrate bevel edge, and chamber interior to avoid the accumulation of polymer byproduct and deposited films and to improve process yield. In an exemplary embodiment, a plasma processing chamber configured to clean a bevel edge of a substrate is provided. The plasma processing chamber includes a substrate support configured to receive the substrate. The plasma processing chamber also includes a bottom edge electrode surrounding the substrate support. The bottom edge electrode and the substrate support are electrically isolated from one another by a bottom dielectric ring. A surface of the bottom edge electrode facing the substrate is covered by a bottom thin dielectric layer. The plasma processing chamber further includes a top edge electrode surrounding a top insulator plate opposing the substrate support. The top edge electrode is electrically grounded.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: November 10, 2015
    Assignee: Lam Research Corporation
    Inventors: Gregory S. Sexton, Andrew D. Bailey, III, Andras Kuthi, Yunsang Kim
  • Patent number: 9184028
    Abstract: A semiconductor wafer processing apparatus includes a first electrode exposed to a first plasma generation volume, a second electrode exposed to a second plasma generation volume, and a gas distribution unit disposed between the first and second plasma generation volumes. The first electrode is defined to transmit radiofrequency (RF) power to the first plasma generation volume, and distribute a first plasma process gas to the first plasma generation volume. The second electrode is defined to transmit RF power to the second plasma generation volume, and hold a substrate in exposure to the second plasma generation volume. The gas distribution unit includes an arrangement of through-holes defined to fluidly connect the first plasma generation volume to the second plasma generation volume. The gas distribution unit also includes an arrangement of gas supply ports defined to distribute a second plasma process gas to the second plasma generation volume.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: November 10, 2015
    Assignee: Lam Research Corporation
    Inventors: Rajinder Dhindsa, Alexei Marakhatnov, Andrew D. Bailey, III