Abstract: A multiple request toggling (MRT) arbitration system for prioritizing requests to a set of shared resources by multiple requestors, especially requests by multiple processors to shared resources in a multiprocessor system. The MRT arbitration system assigns priority to multiple requests on a first-come, first-serve basis with the priority of multiple simultaneous requests being resolved through an arbitration network.

Abstract: Global registers for a multiprocessor system support multiple parallel access paths for simultaneous operations on separate sets of global registers, each set of global registers referred to as a global register file. An arbitration mechanism associated with the global registers is used for resolving multiple, simultaneous requests to a single global register file. An arithmetic and logical unit (ALU) is also associated with each global register file for allowing atomic arithmetic operations to be performed on the entire register value for any of the global registers in that global register file.

Abstract: In a computer which superpositions vector and scalar operations and in which operation results and operands are conducted between buffer registers and functional units on a bidirectional databus system, the result of one or more currently-executing scalar operations can be routed directly to the input of one or more functional units, bypassing the buffer registers and saving computer operational time. A scalar result is routed through a linking apparatus which directly connects a bidirectional databus path on which the scalar result is being conducted to a databus path on which a scalar operand is to be conducted. The routing is conditioned upon identity between the scalar result and operand and upon availability of a databus path to support the scalar operation. If the conditions are not met, the scalar result is conducted to the buffer registers, where it is held until needed or until a databus path is available.

Abstract: A bi-directional databusing system is used in a computer that superposes vector and scalar operations. The computer consists of a main memory, a plurality of pipelined functional units, and a buffer for staging scalar and vector data objects between the main memory and the functional units. The busing system supports two-way data transfer during each of a succession of bus transfer cycles in which data is transferred to the buffer during one phase of a cycle, and from the buffer during a second cycle phase. The busing system includes three sets of bi-directional memory databuses, one for transferring scalar data objects between the main memory and buffer unit, and the other two for transferring vector data objects between the main memory and the buffer.

Abstract: An apparatus is disclosed that translates virtual memory addresses into physical memory addresses. In particular, this apparatus comprises a plurality of rows of content addressable memory cells, a corresponding plurality of random access memory cells and another corresponding plurality of control circuits. The content addressable memory cells store the virtual memory addresses and the random access memory cells store the physical memory addresses. The control circuits are coupled to both the content addressable and the random access memory cells and are disposed for controlling the operation of the apparatus.

Abstract: A new and improved content addressable memory cell is disclosed, which cell stores data supplied on a load data input terminal thereof. The disclosed memory cell is adapted for comparing data supplied on a compare data input terminal thereof with data stored in the cell, and for supplying an output signal on a match data output terminal when the compare data is the same as the data stored in the cell. A latch circuit is employed as the storage element of the cell. First and second means are each coupled between a reference potential and the match data output terminal, which means are operative in response to the state of the latch circuit and the compare data supplied on the compare data input terminal.

Abstract: A new and improved shifter circuit for multiplexing bytes of data into various orders on a finite size bus is disclosed. The improved shifter circuit includes an array of barrel shifter circuits arranged into N groups of M shifter circuits per group wherein each shifter circuit has P data input terminals and P output terminals. The letters N, M and P represent integers. Each of the P output terminals of each of the M shifter circuits in a group are coupled to one another, respectively, so as to form N.times.P output terminals of the array.