Patents by Inventor Andrew F. Glew

Andrew F. Glew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5854914
    Abstract: A method and apparatus for executing a misaligned load. The method begins with receiving a load request to load data from a first memory location. An entry in a store buffer is tested to determine whether the entry corresponds to the first memory location. The entry is also tested to determine whether the entry corresponds to a second memory location subsequent to the first memory location. The load request is blocked if the entry corresponds to the first memory location or the second memory location. After a store operation for the store buffer entry is executed, the load request may be unblocked. The apparatus is a processor or a computer system comprising a load buffer capable of storing a load request address in response to a load request. The processor includes an incrementing circuit that generates an incremented load request address. The processor also includes a store buffer containing a portion of a store request address.
    Type: Grant
    Filed: September 10, 1996
    Date of Patent: December 29, 1998
    Assignee: Intel Corporation
    Inventors: Milind Bodas, Glenn J. Hinton, Andrew F. Glew
  • Patent number: 5852726
    Abstract: A method and apparatus for executing floating point and packed data instructions using a single physical register file that is aliased. According to one aspect of the invention, a processor is provided that includes a decode unit, a mapping unit, and a storage unit. The decode unit is configured to decode instructions and their operands from at least one instruction set including at least a first and second set of instructions. The storage unit includes a physical register file. The mapping unit is configured to map operands used by the first set of instructions to the physical register file in a stack referenced manner. In addition, the mapping unit is configured to map operands used by the second set of instructions to the same physical register file in a non-stack reference manner.
    Type: Grant
    Filed: December 19, 1995
    Date of Patent: December 22, 1998
    Assignee: Intel Corporation
    Inventors: Derrick Lin, Romamohan R. Vakkalagadda, Andrew F. Glew, Larry M. Mennemeier, Alexander D. Peleg, David Bistry, Millind Mittal, Carole Dulong, Eiichi Kowashi, Benny Eitan
  • Patent number: 5835748
    Abstract: A method and apparatus for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file. According to one aspect of the invention, a processor is provided that includes at least two physical register files--one for executing scalar data type operations and the other for executing packed data type operations. In addition, the processor includes a transition unit that is configured to cause the two physical register files to logically appear to software executing on the processor as a single logical register file.
    Type: Grant
    Filed: December 19, 1995
    Date of Patent: November 10, 1998
    Assignee: Intel Corporation
    Inventors: Doron Orenstein, Ofri Wechsler, Millind Mittal, Andrew F. Glew, Larry M. Mennemeier, Alexander D. Peleg, David Bistry, Carole Dulong, Eiichi Kowashi, Benny Eitan, Derrick Lin, Ramamohan R. Vakkalagadda
  • Patent number: 5826094
    Abstract: A mechanism for indicating within a register alias table (RAT) that certain data has become architecturally visible so that the RAT contains the most recent location of the certain data. Upon receiving the indication that data associated with a particular register is architecturally visible, if a subsequent operation uses the particular register as a source, the data will be supplied from the architecturally visible buffer instead of from an internal buffer (not architecturally visible). The internal buffer is implemented by a reorder buffer (ROB) which contains information associated with instructions that have not yet retired. The architecturally visible buffer is a retirement register file (RRF) which contains information associated with retired instructions.
    Type: Grant
    Filed: July 8, 1996
    Date of Patent: October 20, 1998
    Assignee: Intel Corporation
    Inventors: Robert P. Colwell, David B. Papworth, Michael A. Fetterman, Andrew F. Glew, Glenn J. Hinton
  • Patent number: 5826109
    Abstract: The present invention provides for executing load instructions with a processor having a non-blocking cache memory, wherein individual load operations are dispatched to the cache memory and the cache memory signals the prevent the load operation from being sent to external memory when the load operation misses the cache memory and there is already a currently pending bus cycle to the same cache line. This helps reduce bus traffic on the external bus.
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: October 20, 1998
    Assignee: Intel Corporation
    Inventors: Jeffery M. Abramson, Haitham Akkary, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland, David B. Papworth, Robert W. Martell
  • Patent number: 5819079
    Abstract: A computer system includes an instruction prefetching mechanism that detects whether an instruction to be prefetched is located in a region of memory that is uncacheable. To perform an instruction prefetch, an instruction fetch unit (IFU) receives an instruction pointer indicating a memory location containing an instruction to be prefetched. The instruction pointer may be provided by a branch target buffer (BTB) as a result of a branch prediction, or by auxiliary branch prediction mechanisms, or actual execution. The IFU accesses an instruction translation look-aside buffer (ITLB) to determine both the physical address corresponding to the linear address of the instruction pointer and to determine an associated memory type stored therein. If the memory type indicates an uncacheable memory location, the IFU waits until all previous executed instructions have completed. The IFU does this by inserting a "permission-to-fetch" instruction, and then stalling.
    Type: Grant
    Filed: September 11, 1995
    Date of Patent: October 6, 1998
    Assignee: Intel Corporation
    Inventors: Andrew F. Glew, Ashwani Gupta
  • Patent number: 5809271
    Abstract: A simplified method and apparatus for handling the change of instruction control flow in a microprocessor is provided. Rather than attempting to implement a change in the instruction flow immediately, the processor first recognizes that flow is to be redirected from a predicted instruction flow to a correct instruction flow according to a flow control indicator. The flow control indicator may be attached to instructions flowing down the pipeline or inserted as a separate instruction in the pipeline. The pipeline is cleared of state created by instructions that do not follow the correct instruction flow, i.e., instructions that were erroneously fetched after the instruction causing the change in flow. The change in flow as indicated by the flow control indicator is implemented later in the pipeline.
    Type: Grant
    Filed: August 23, 1995
    Date of Patent: September 15, 1998
    Assignee: Intel Corporation
    Inventors: Robert P. Colwell, Atiq Bajwa, Michael A. Fetterman, Andrew F. Glew, Glenn J. Hinton, David B. Papworth
  • Patent number: 5796637
    Abstract: A system for filtering multiple event signals from multiple event-generating sources. A selection circuit receives the multiple event signals and selects one of the event signals. A filter circuit is coupled to the selection circuit and receives the selected event signal from the selection circuit. The filter circuit produces a filtered event signal. A counter receives the filtered event signal from the filter circuit and is incremented in response to the filtered event signal. The filter circuit includes a comparison logic circuit and an edge detection logic circuit.
    Type: Grant
    Filed: September 6, 1996
    Date of Patent: August 18, 1998
    Assignee: Intel Corporation
    Inventors: Andrew F. Glew, Sumeet Agrawal, Kamla P. Huck, Patrick G. Franklin
  • Patent number: 5778407
    Abstract: A circuit comprising a number of range registers and complimentary decoding/matching circuits is provided to a processor for determining the memory type of a physical address, thereby allowing memory operating characteristics to be determined as soon as the physical address is available in an execution stage preceding cache access. Additionally, a memory type field is provided to each address translation lookaside buffer entry of the data and instruction memory subsystem for storing the determined memory type, and the memory type determination circuit is disposed in the page miss handler, thereby allowing memory type to be determined at the same time when the physical address is determined.
    Type: Grant
    Filed: June 21, 1996
    Date of Patent: July 7, 1998
    Assignee: Intel Corporation
    Inventors: Andrew F. Glew, Glenn J. Hinton, David B. Papworth, Michael Alan Fetterman, Robert P. Colwell, Frederick Jay Pollack
  • Patent number: 5778245
    Abstract: A method and apparatus for dynamically allocating entries of microprocessor resources to particular instructions in an efficient manner to efficiently utilize buffer size and resources. The pipelined and superscalar microprocessor is capable of speculatively executing instructions and also out-of-order processing. Resources within the microprocessor include a store buffer, a load buffer, a reorder buffer and a reservation station. The reorder buffer contains a larger set of physical registers and also contains information related to speculative instructions and the reservation station comprises information related to instructions pending execution. The load buffer is only allocated to load instructions and is valid for an instruction from allocation pipestage to instruction retirement. The store buffer is only allocated to store instructions and is valid for an instruction from allocation to store performance.
    Type: Grant
    Filed: March 1, 1994
    Date of Patent: July 7, 1998
    Assignee: Intel Corporation
    Inventors: David B. Papworth, Andrew F. Glew, Glenn J. Hinton, Robert P. Colwell, Michael A. Fetterman, Shantanu R. Gupta, James S. Griffith
  • Patent number: 5751983
    Abstract: A method and apparatus for speculatively dispatching and/or executing LOADs in a computer system includes a memory subsystem of a out-of-order processor that handles LOAD and STORE operations by dispatching them to respective LOAD and STORE buffers in the memory subsystem. When a LOAD is subsequently dispatched for execution, the store buffer is searched for STOREs having unknown addresses. If any STOREs are found which are older than the dispatched LOAD, and which have an unknown address, the LOAD is tagged with an unknown STORE address identification (USAID). When a STORE is dispatched for execution, the LOAD buffer is searched for loads that have been denoted as mis-speculated loads. Mis-speculated loads are prevented from corrupting the architectural state of the machine with invalid data.
    Type: Grant
    Filed: October 3, 1995
    Date of Patent: May 12, 1998
    Inventors: Jeffrey M. Abramson, David B. Papworth, Haitham H. Akkary, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland
  • Patent number: 5751986
    Abstract: A computer system including a processor having a inherently weakly-ordered memory model comprising a mechanism for emulating strong-ordering to produce self-consistent ordering on a system-wide basis. The processor snoops the system bus externally to determine if a STORE on the external bus hits a LOAD buffer inside the memory subsystem of the processor. If so, the situation is flagged as one which carries the risk of violating processor ordering rules. When the STORE hits the same LOAD address in the LOAD buffer of the processor's memory subsystem, the speculative state of the processor is erased. This cancels the LOAD operation in all subsequent operations. The processor then begins executing from the aborted LOAD; this time loading the newly updated value.
    Type: Grant
    Filed: January 3, 1997
    Date of Patent: May 12, 1998
    Assignee: Intel Corporation
    Inventors: Michael A. Fetterman, Glenn J. Hinton, David B. Papworth, Andrew F. Glew, Robert P. Colwell
  • Patent number: 5751996
    Abstract: A memory-type value identifying the type of memory contained with a range of memory locations is explicitly stored within a microprocessor. Prior to processing a memory micro-instruction such as a load or store, the memory-type is determined for the memory location identified by the memory micro-instruction. Once the memory-type is known the memory micro-instruction is processed in accordance with any one of a number of processing protocols including write-through processing, write-back processing, write-protect processing, restricted-cacheability processing, uncacheable speculatable write-combining processing, or uncacheable processing. By providing memory-type information explicitly within the microprocessor, the type of memory identified by a micro-instruction is known before the micro-instruction is processed. Accordingly, the protocol by which the micro-instruction is processed may be efficiently tailored to the memory-type.
    Type: Grant
    Filed: December 17, 1996
    Date of Patent: May 12, 1998
    Assignee: Intel Corporation
    Inventors: Andrew F. Glew, Glenn J. Hinton
  • Patent number: 5748937
    Abstract: A computer system having a mechanism for maintaining processor ordering during out-of-order instruction execution is disclosed wherein load memory instructions are accessed according to program order and executed out-of-order in relation to the program order where appropriate. Processors in the system snoop an external bus for bus transactions that conflict with completed load memory instructions before committing results of the completed load memory instructions to an architectural state.
    Type: Grant
    Filed: March 28, 1997
    Date of Patent: May 5, 1998
    Assignee: Intel Corporation
    Inventors: Jeffrey M. Abramson, Haitham Akkary, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland
  • Patent number: 5749084
    Abstract: A processor having an address generation unit (AGU) for generating an address corresponding to an entry that is to be fetched. The AGU includes a segment register file for storing address segments, and a circuit for rearranging noncontiguous base and limit bit positions of a first address segment in order to generate a second address segment having all base and limit bits in a contiguous order. The AGU further includes a circuit for executing a single microinstruction to perform read and write operations on a selected field of the second address segments stored in the segment register file.
    Type: Grant
    Filed: April 17, 1996
    Date of Patent: May 5, 1998
    Assignee: Intel Corporation
    Inventors: Kamla P. Huck, Scott D. Rodgers, Andrew F. Glew
  • Patent number: 5740393
    Abstract: A method for enforcing an instruction pointer limit in a processor, wherein a retire circuit determines a speculative instruction pointer for a set of retiring instruction during a retirement operation. The retire circuit also determines whether each speculative instruction pointer exceeds the instruction pointer limit. The retire circuit commits the result data value of each instruction to the architectural state if the speculative instruction pointer for the result data value does not exceed the instruction pointer limit.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: April 14, 1998
    Assignee: Intel Corporation
    Inventors: Rohit A. Vidwans, Darrell D. Boggs, Michael A. Fetterman, Andrew F. Glew
  • Patent number: 5729728
    Abstract: A simplified method and apparatus for handling the change of instruction control flow in a microprocessor is provided. Rather than attempting to implement a change in the instruction flow immediately, the processor first recognizes that flow is to be redirected from a predicted instruction flow to a correct instruction flow according to a flow control indicator. The flow control indicator may be attached to instructions flowing down the pipeline or inserted as a separate instruction in the pipeline. The pipeline is cleared of state created by instructions that do not follow the correct instruction flow, i.e., instructions that were erroneously fetched after the instruction causing the change in flow. The change in flow as indicated by the flow control indicator is implemented later in the pipeline.
    Type: Grant
    Filed: September 6, 1996
    Date of Patent: March 17, 1998
    Assignee: Intel Corporation
    Inventors: Robert P. Colwell, Atiq Bajwa, Michael A. Fetterman, Andrew F. Glew, Glenn J. Hinton, David B. Papworth
  • Patent number: 5727176
    Abstract: A data processor includes a plurality of physical registers and a decoder that decodes a stream of instructions into micro-operations which include speculative operations specifying associated logical registers. The data processor further includes a register-alias table having a plurality of addressable entries corresponding to logical registers, specified by the speculative operations. Each entry of the register-alias table contains a register pointer to a corresponding physical register. The processor further includes a retirement register file that maintains register values of non-speculative operations, and a retirement array that maintains a retirement ordering for the retirement register file. Both the register-alias table and retirement array are updated by circuitry that is responsive to a register exchange operation; the circuitry swapping register pointers associated with first and second entries, respectively.
    Type: Grant
    Filed: March 6, 1996
    Date of Patent: March 10, 1998
    Assignee: Intel Corporation
    Inventors: David W. Clift, James M. Arnold, Robert P. Colwell, Andrew F. Glew
  • Patent number: 5724536
    Abstract: A method and apparatus for performing load operations in a computer system. The present invention includes a method and apparatus for dispatching the load operation to be executed. The present invention halts the execution of the load operation when a dependency exists between the load operation and another memory operation currently pending in the system. When the dependency no longer exists, the present invention redispatches the load operation so that it completes.
    Type: Grant
    Filed: January 4, 1994
    Date of Patent: March 3, 1998
    Assignee: Intel Corporation
    Inventors: Jeffery M. Abramson, Haitham Akkary, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland
  • Patent number: 5721857
    Abstract: A method is provided for recovering the effective address of memory instructions in an out-of-order microprocessor for use by an exception handler upon the occurrence of one of an exception and a systems management interrupt. The microprocessor comprises at least one execution unit for executing a plurality of instructions out-of-order and a re-order buffer having storage locations for buffering result data produced from the execution of the plurality of instructions. Each instruction is associated with a location designator to identify a unique storage location within the re-order buffer in which the result data for an executed instruction is written. The microprocessor further comprises a memory order buffer having storage locations for buffering memory instructions waiting for access to memory for execution, these storage locations also being identified by corresponding location designators.
    Type: Grant
    Filed: May 22, 1996
    Date of Patent: February 24, 1998
    Assignee: Intel Corporation
    Inventors: Andrew F. Glew, Jeffrey M. Abramson, Kris G. Konigsfeld, Atiq Bajwa, Warren R. Morrow, William C. Alexander, III