Abstract: A method is provided for recovering the effective address of memory instructions in an out-of-order microprocessor for use by an exception handler upon the occurrence of one of an exception and a systems management interrupt. The microprocessor comprises at least one execution unit for executing a plurality of instructions out-of-order and a re-order buffer having storage locations for buffering result data produced from the execution of the plurality of instructions. Each instruction is associated with a location designator to identify a unique storage location within the re-order buffer in which the result data for an executed instruction is written. The microprocessor further comprises a memory order buffer having storage locations for buffering memory instructions waiting for access to memory for execution, these storage locations also being identified by corresponding location designators.

Abstract: A pipelined method for executing instructions in a computer system. The present invention includes providing multiple instructions as a continuous stream of operations. This stream of operations is provided in program order. In one embodiment, the stream of operations is provided by performing an instruction cache memory lookup to fetch the multiple instructions, performing instruction length decoding on the instructions, rotating the instructions, and decoding the instructions. The present invention also performs register renaming, allocates resources and sends a portion of each of the operations to a buffering mechanism (e.g., a reservation station). The instruction cache memory lookup, instruction length decoding, rotation and decoding of the instructions, as well as the register renaming, are performed in consecutive pipestages.The present invention provides for executing the instructions in an out-of-order pipeline. The execution produces results.

Abstract: A method and apparatus for performing operations with a processor in a computer system. Load operations are performed by use of a dispatch pipeline and a memory execution pipeline. The dispatch pipeline dispatches the load operation for execution by the processor, while the memory execution pipeline controls the execution of the load operation to memory. The present invention reduces the latency involved in executing a load operation by coupling the execution of the two pipelines during execution of the load operation.

Abstract: A memory operation is issued in a processor. Upon detecting both that the memory operation produces a code segment violation and that the memory operation is blocked at retirement, a blocking signal is produced to block a bus access responsive to the memory operation. A second signal signifies that the memory operation completed.

Abstract: A method for executing different sets of instructions that cause a processor to perform different data type operations in a manner that is invisible to various operating system techniques, that promotes good programming practices, and that is invisible to existing software conventions. According to one aspect of the invention, a data processing apparatus executes a first set of instructions of a first instruction type on what at least logically appears to software as a single logical register file. While the data processing apparatus is executing the first set of instructions, the single logical register file appears to be operated as a flat register file. In addition, the data processing apparatus executes a first instruction of a second instruction type using the logical register file. However, while the data processing apparatus is executing the first instruction, the logical register file appears to be operated as a stack referenced register file.

Abstract: Code breakpoint detection logic for a superscalar microprocessor. Superscalar operation in a microprocessor is maintained with a single breakpoint detection mechanism which performs breakpoint detection prior to instruction decoding. One bit for each byte in an instruction packet is provided as a result of a comparison of the aligned instruction fetch to the debug registers. After decoding, if the first byte of an instruction has an appended breakpoint true bit, then an event is signaled for breakpoint handling by the superscalar microprocessor.

Abstract: A method and apparatus for dispatching load operations in a computer system. The present invention includes a method and apparatus for determining when the load operation is ready for dispatched to memory. The load operation is then scheduled to dispatch from memory and then dispatched to memory. In the present invention, a load is determined ready when it is no longer blocked, such that there is no condition which produces a resource or address dependency causing the load to be blocked.

Abstract: A method and apparatus for instruction refetch in a processor is provided. To ensure that a macro instruction is available for refetching after the processor has handled an event or determined a correct restart address after a branch misprediction, an instruction memory includes an instruction cache for caching macro instructions to be fetched, and a victim cache for caching victims from the instruction cache. To ensure the availability of a macro instruction for refetching, the instruction memory (the instruction cache and victim cache together) always stores a macro instruction that may need to be refetched until the macro instruction is committed to architectural state. A marker micro instruction is inserted into the processor pipeline when an instruction cache line is victimized. The marker specifies an entry in the victim cache occupied by the victimized cache line.

Abstract: A data cache and a plurality of companion fill buffers having corresponding tag matching circuitry are provided to a computer system. Each fill buffer independently stores and tracks a replacement cache line being filled with data returning from main memory in response to a cache miss. When the cache fill is completed, the replacement cache line is output for the cache tag and data arrays of the data cache if the memory locations are cacheable and the cache line has not been snoop hit while the cache fill was in progress. Additionally, the fill buffers are organized and provided with sufficient address and data ports as well as selectors to allow the fill buffers to respond to subsequent processor loads and stores, and external snoops that hit their cache lines while the cache fills are in progress.

Abstract: A data cache and a plurality of companion fill buffers having corresponding tag matching circuitry are provided to a computer system. Each fill buffer independently stores and tracks a replacement cache line being filled with data returning from main memory in response to a cache miss. When the cache fill is completed, the replacement cache line is output for the cache tag and data arrays of the data cache if the memory locations are cacheable and the cache line has not been snoop hit while the cache fill was in progress. Additionally, the fill buffers are organized and provided with sufficient address and data ports as well as selectors to allow the fill buffers to respond to subsequent processor loads and stores, and external snoops that hit their cache lines while the cache fills are in progress.

Abstract: A method and apparatus for performing store operations that includes calculating the address and obtaining the data for the store operation. The address represents the memory location to which the data is to be stored. Once the address is calculated and the data obtained, the store operation is committed to processor state. The store operation may be dispatched to memory to complete the execution of the store operation.

Abstract: In a microprocessor, an apparatus and method for performing memory functions and issuing bus cycles. Special microinstructions are stored in microcode ROM. These microinstructions are used to perform the memory functions and to generate the special bus cycles. Initially, an address corresponding to a requested operation to be performed is generated for one of these special microinstructions. That special microinstruction, along with its address, is then transmitted over the bus to the various units of the microprocessor. When each of the units receives the microinstruction, it determines whether that microinstruction is to be ignored based on the address. If a particular unit ignores the microinstruction, the microinstruction is forwarded to subsequent units in the pipeline for processing. Otherwise, if that particular unit performs the requested operation as specified by the microinstruction's address.

Abstract: A microprocessor having a bus for the transmission of data, an execution unit for processing data and instructions, a memory for storing data and instructions, and a write combining buffer for combining data of at least two write commands into a single data set, wherein the combined data set is transmitted over the bus in one clock cycle rather than two or more clock cycles. Thereby, buss traffic is minimized. The write combining buffer is comprised of a single line having a 32-byte data portion, a tag portion, and a validity portion. The tag entry specifies the address corresponding to the data currently stored in the data portion. There is one valid bit corresponding to each byte of the data portion which specifies whether that byte currently contains useful data. So long as subsequent write operations to the write combining buffer result in hits, the data is written to the buffer's data portion. But when a miss occurs, the line is reallocated, and the old data is written to the main memory.

Abstract: A speculative execution out of order processor comprising a reorder circuit containing a plurality of physical registers that buffer speculative execution results for integer and floating-point operations, and a real register circuit containing a plurality of committed state registers that buffer committed execution results for either integer or floating-point operations, depending on the register. The reorder and real register circuits read the speculative and committed source data values for incoming micro-ops, and transfer the speculative and committed source data values over to a micro-op dispatch circuit over a common data path. A retire logic circuit commits the speculative execution results to an architectural state by transferring the speculative execution results from the reorder circuit to the real register circuit.

Abstract: A processor providing a redundant intermediate form of a result in fewer than the total number of clock cycles needed to calculate a final complete result. The redundant form is forwarded to subsequent instructions or operations capable of utilizing the redundant intermediate form to enhance the performance of the processor.

Abstract: Register identification preservation in a microprocessor implementing register renaming. Multiplexing and control circuitry are implemented for manipulating data sources to be supplied to a microprocessor's functional units. The circuitry will generate zero extending for source data to an execution unit where a data source register specified is shorter than a general register size utilized by the microprocessor. Similarly, the multiplexing and control circuitry will shift bits of data from one location to another upon a source input to a functional unit in accordance with control signals designating such activity.

Abstract: A translation lookaside buffer is described for use with a microprocessor capable of speculative and out-of-order processing of memory instructions. The translation lookaside buffer is non-blocking in response to translation lookaside buffer misses requiring page table walks. Once a translation lookaside buffer miss is detected, a page table walk is initiated to satisfy the miss. During the page table walk, additional memory instructions are processed by the translation lookaside buffer. Any additional instructions which cause translation lookaside buffer hits are merely processed by the translation lookaside buffer. However, instructions causing translation lookaside buffer misses while the page table walk is being performed are blocked pending completion of the page table walk. Once the page table walk is completed the blocked instructions are reawakened and are again processed by the translation lookaside buffer. Global and selective wakeup mechanisms are described.

Abstract: A Register Alias Table (RAT) for floating point and integer register renaming within a superscalar microprocessor. The RAT provides register renaming of integer and floating point registers and flags to take advantage of a larger physical register set than would ordinarily be available within a given macroarchitecture (such as the Intel architecture or Power PC or Alpha designs) and thereby eliminate false data dependencies that reduce overall superscalar processing performance. As uops are simultaneously presented to the RAT logic, their logical sources (both floating point and integer) are used as indices into a RAT array to look up the corresponding physical registers which reside within a Re-Order Buffer (ROB) where the data for these logical source is found. The ROB is composed of many multiple-bit physical registers. During the same clock cycle, the RAT array is updated with new physical destinations granted by an Allocator such that uops in future cycles can read them for their physical sources.

Abstract: Store forwarding circuitry is provided to an out-of-order execution processor having a store buffer of buffered memory store operations. The store forwarding circuitry conditionally forwards store data for a memory load operation from a variable subset of the buffered memory store operations that is functionally dependent on the time the memory load operation is issued, taking into account the execution states of these buffered memory store operations. The memory load operation may be issued speculatively and/or executed out-of-order. The execution states of the buffered memory store operations may be speculatively executed or committed. The data and address aspects of the memory store operations may be executed separately.

Abstract: Pipeline lengthening in functional units likely to be involved in a writeback conflict is implemented to avoid conflicts. Logic circuitry is provided for comparing the depths of two concurrently executing execution unit pipelines to determine if a conflict will develop. When it appears that two execution units will attempt to write back at the same time, the execution unit having a shorter pipeline will be instructed to add a stage to its pipeline, storing its result in a delaying buffer for one clock cycle. After the conflict has been resolved, the instruction to lengthen the pipeline of a given functional unit will be rescinded. Multistage execution units are designed to signal a reservation station to delay the dispatch of various instructions to avoid conflicts between execution units.