Abstract: A microprocessor comprising an execution unit for performing arithmetic functions, a fetch unit for determining which entry is to be accessed, an issue unit for accessing the entry from storage in a memory, and an address generation unit for generating an address for that entry. Portions of the base and limit values used for generating the address are stored in separate segments. These separate portions are rearranged so as to form a segment having contiguous base and limit bits. The contiguous base and limit values are then stored in a register file. Copies of the base and limit are stored in control registers and broadcast to other units. Furthermore, a resettable null bit is stored in another register. In addition, the AGU includes a means for selecting a particular field of the register file and performing read/write operations on the selected file.

Abstract: In an out-of-order execution computer system, a store buffer is conditionally signaled to output buffered store data of buffered memory store operations, when a buffered memory load operation is being executed. The determination on whether to signal the store buffer or not is made using control information that includes the allocation state of the store buffer at the time the memory load operation being executed was issued. The allocation state includes the identification of the buffer slot storing the last memory store operation stored into the store buffer, and the wraparound state of a circular wraparound allocation approach employed to allocate buffer slots to the memory store operations, at the time the memory load operation being executed was issued.

Abstract: An allocator assigns entries for a circular buffer. The allocator receives requests for storing data in entries of the circular buffer, and generates a head pointer to identify a starting entry in the circular buffer for which circular buffer entries are not allocated. In addition to pointing to an entry in the circular buffer, the head pointer includes a wrap bit. The allocator toggles the wrap bit each time the allocator traverses the linear queue of the circular buffer. A tail pointer is generated, including the wrap bit, to identify an ending entry in the circular buffer for which circular buffer entries are allocated. In response to the request for entries, the allocator sequentially assigns entries for the requests located between the head pointer and the tail pointer. The allocator has application for use in a microprocessor performing out-of-order dispatch anti speculative execution. The allocator is coupled to a reorder buffer, configured as a circular buffer, to permit allocation of entries.

Abstract: An allocator assigns entries for a circular buffer. The allocator receives requests for storing data in entries of the circular buffer, and generates a head pointer to identify a starting entry in the circular buffer for which circular buffer entries are not allocated. In addition to pointing to an entry in the circular buffer, the head pointer includes a wrap bit. The allocator toggles the wrap bit each time the allocator traverses the linear queue of the circular buffer. A tail pointer is generated, including the wrap bit, to identify an ending entry in the circular buffer for which circular buffer entries are allocated. In response to the request for entries, the allocator sequentially assigns entries for the requests located between the head pointer and the tail pointer. The allocator has application for use in a microprocessor performing out-of-order dispatch and speculative execution. The allocator is coupled to a reorder buffer, configured as a circular buffer, to permit allocation of entries.

Abstract: A branch prediction mechanism that maintains both speculative history and actual history for each branch instruction in a branch target buffer. The actual branch history contains the branch history for fully resolved occurrences of the branch instruction. The speculative branch history contains the actual history plus the "history" of recent branch predictions for the branch. If the speculative branch history contains any recent predictions, then a speculation bit is set. When the speculation bit is set, this indicates that there is speculative history for a branch. Therefore, when the speculation bit is set the speculative history is used to make branch predictions. If a misprediction is made for the branch, the speculation bit is cleared since the speculative history contains inaccurate branch history.

Abstract: A number of data misalignment detection circuits are provided to select ones of an execution unit and memory order interface components, of an out-of-order (OOO) execution computer system, this aids the buffering and fault generation circuits of the memory order interface components, to buffer and dispatch load and store operations depending on if the misalignments are detected and their nature, resulting in load and store operations of misaligned data against a memory subsystem of the OOO execution computer system are available, the data addressed by the load and store operations are of the following types: chunk split, cache split, or page split misaligned.

Abstract: A hybrid execution unit for executing miscellaneous instructions in a single clock cycle. The execution unit receives either integer or floating point data, and performs manipulations of two incoming sources to produce a result source in conjunction with existing integer and floating point execution units.

Abstract: A non-blocking translation lookaside buffer is described for use in a microprocessor capable of processing speculative and out-of-order instructions. Upon the detection of a fault, either during a translation lookaside buffer hit or a page table walk performed in response to a translation lookaside buffer miss, information associated with the faulting instruction is stored within a fault register within the translation lookaside buffer. The stored information includes the linear address of the instruction and information identifying the age of instruction. In addition to storing the information within the fault register, a portion of the information is transmitted to a reordering buffer of the microprocessor for storage therein pending retirement of the faulting instruction. Prior to retirement of the faulting instruction, the translation lookaside buffer continues to process further instructions.

Abstract: Register identification preservation in a microprocessor implementing register renaming. Multiplexing and control circuitry are implemented for manipulating data sources to be supplied to a microprocessor's functional units. The circuitry will generate zero extending for source data to an execution unit where a data source register specified is shorter than a general register size utilized by the microprocessor. Similarly, the multiplexing and control circuitry will shift bits of data from one location to another upon a source input to a functional unit in accordance with control signals designating such activity.

Abstract: A circuit comprising a number of address range registers and complimentary decoding/matching circuits is provided to a processor for determining the memory type of a physical address, thereby allowing memory type to be determined as soon as the physical address is available in an execution stage preceding cache access. Additionally, a memory type field is provided to each address translation lookaside buffer entry of the data and instruction memory subsystem for storing the determined memory type. The memory type determination circuit is disposed in the page miss handler, thereby allowing memory type to be determined at the same time when the physical address is determined.

Abstract: A bypass mechanism within a register alias table unit (RAT) for handling source-destination data dependencies between operands of a given set of operations issued simultaneously within a superscalar microprocessor. Operations of the given set are presented in program order and data dependencies occur when a source register of particular operation is also utilizes as a destination register of a preceding operation within the given set of operations. At this occurrence, the initial read of the RAT unit will not have supplied the most current rename of the source register. The present invention includes a comparison mechanism to detect this condition. Also included is a bypass mechanism for bypassing the physical source register output by the initial read of the RAT unit with a recently allocated physical destination register assigned to the preceding operation having the matched physical destination register.

Abstract: An instruction dispatch circuit is disclosed that improves instruction execution throughput for a processor. The instruction dispatch circuit comprises an instruction buffer with a plurality of instruction entries and a content addressable memory array having at least one cam entry corresponding to each instruction entry. Each cam entry stores at least one source tag for the corresponding instruction entry. The content addressable memory array matches to a result tag from an execution circuit over a result bus, wherein the execution circuit transfers the result tag over the result bus at least one clock cycle before transferring a corresponding result data value over the result bus. Each cam entry generates a cam match signal used to determine whether data dependent instruction are ready for dispatch.

Abstract: The data cache unit includes a separate fill buffer and a separate write-back buffer. The fill buffer stores one or more cache lines for transference into data cache banks of the data cache unit. The write-back buffer stores a single cache line evicted from the data cache banks prior to write-back to main memory. Circuitry is provided for transferring a cache line from the fill buffer into the data cache banks while simultaneously transferring a victim cache line from the data cache banks into the write-back buffer. Such allows the overall replace operation to be performed in only a single clock cycle. In a particular implementation, the data cache unit is employed within a microprocessor capable of speculative and out-of-order processing of memory instructions. Moreover, the microprocessor is incorporated within a multiprocessor computer system wherein each microprocessor is capable of snooping the cache lines of data cache units of each other microprocessor. The data cache unit is also a non-blocking cache.

Abstract: A bypass mechanism within a register alias table unit (RAT) for handling source-destination dependencies between operands of a given set of operations issued simultaneously within a superscalar microproessor. Operations of the given set are presented in program order and data dependencies occur when a source register of particular operation is also utilizes as a destination register of a preceding operation within the given set of operations. At this occurence, the initial read of the RAT unit will not have supplied the most current rename of the source register. The present invention includes a comparison mechanism to detect this condition. Also included is a bypass mechanism for bypassing the physical source register output by the initial read of the RAT unit with a recently allocated physical destination register assigned to the preceding operation having the matched physical destination register.

Abstract: A microprocessor contains an address generation unit, including a segment block, for loading descriptor data and a segment selector in a segment register. Two descriptor loads from a global descriptor table (GDT) and a local descriptor table (LDT) are executed. A 64 bit global descriptor from the GDT is loaded into a temporary register, and a 64 bit local descriptor from the LDT is also loaded into a separate temporary register. If a table indicator bit in the segment selector indicates use of the GDT, then the descriptor data from the GDT is selected. Alternatively, if the table indicator bit in the segment selector indicates the use of the LDT, then the descriptor data from the LDT is selected. The segment block splits the 64 bit descriptor data selected into two 32 bit quantities. The two 32 bit data quantities are input to a test programmable logic array (PLA). The test PLA checks for permission violations, or faults, and detects the need for special handling of the register segment load operation.

Abstract: A Register Alias Table (RAT), including a retirement floating point RAT array, for floating point register renaming within a superscalar microprocessor capable of speculative execution. The RAT provides register renaming floating point registers to take advantage of a larger physical register set than would ordinarily be available within a given macroarchitecture's logical register set (such as the Intel architecture or PowerPC or Alpha designs) and thereby eliminate false data dependencies that reduce overall superscalar processing performance. As a set of uops is presented to the floating point RAT logic, their logical sources are used as indices into a floating point RAT array to look up the corresponding physical registers which reside within a Re-Order Buffer (ROB) where the data for these logical sources is found.

Abstract: A high byte right-shift detection mechanism with a register alias table unit (RAT) for selectively causing right-shifting of high byte physical source register data before operations are executed within a microprocessor is described. A high byte right-shift condition occurs when a logical source register that is presented to the RAT for renaming is a high byte register and the corresponding physical source register selected by the RAT is not right-adjusted. A non right-adjusted physical source register is detected when either the physical source register is an architectural state register or the physical source register is a larger width register that includes the renamed high byte register.

Abstract: A register alias table unit (RAT) with an idiom recognition mechanism for overriding partial width conditions stalls is described. A partial width stall condition occurs during the RAT renaming process when a logical source register being renamed is larger than the corresponding physical source register pointed to by a renaming table. An idiom recognizer detects uops that zero their logical destination register and sets and clears zero bits in an iRAT array accordingly. The zero bits indicate which portions of an entry's physical source register are known to be zeros. A partial width stall override mechanism overrides a partial width stall condition when the zero bits for the physical source register causing the partial width stall indicate that the "missing" portion of the physical source register contains zeros. The performance of a microprocessor implementing such a RAT renaming mechanism with an idiom recognizer is improved because common partial width stalls are avoided.

Abstract: Instructions are fetched and issued by an instruction fetch and issue circuit with the instructions' sizes in program order. An allocate circuit allocates reservation station entries in a reservation station circuit, and reorder buffer entries in a reorder circuit, for the issued instructions in order, storing the instructions' sizes in the allocated reorder buffer entries. The reservation and dispatch circuit dispatches the issued instructions to the execution circuits for execution when they are ready. The execution circuits store the result data including target addresses of branch instructions into the corresponding reorder buffer entries. During each retirement operation, a retire circuit reads the instruction sizes and the target addresses for a predetermined number of issued instructions from their allocated reorder buffer entries.

Abstract: A mechanism for coordinating source data in a processor, wherein a decode circuit issues instructions comprising at least one immediate valid flag and at least one logical register source. The immediate valid flag indicates whether an immediate operand for the instruction is available on an immediate data bus, and the logical register source specifies a physical register or a committed state register. A speculative result data value and a speculative source valid flag are read from the physical register, and a committed result data value is read from the committed state register. The speculative result data value and the speculative source valid flag or the committed result data value and the committed source valid flag provide a source data value and a source data valid flag for scheduling an execution of the instruction.