Abstract: The described embodiments include a computing device with multiple interrupt processors for processing interrupts. In the described embodiments, each of the multiple processors is classified as one or more processor types based on factors such as features and functionality of the processor, an operating environment of the processor, the characteristics of some or all of the available interrupts, etc. During operation, an interrupt controller in the computing device receives an indication of an interrupt. The interrupt controller then determines a processor type for processing the interrupt. Next, the interrupt controller causes the interrupt to be processed by one of the plurality of processors that is the determined processor type.

Abstract: The described embodiments include a computing device that performs operations for at least one of resizing or relocating a table in a memory in the computing device. In the described embodiments, the computing device includes at least one register storing a table base address indicating an original location of an original table in the memory and a table size indicating an original size of the original table in the memory. When relocating the original table, the computing device copies, using the table base address, some or all of the entries from the original table to a new table in the memory and then updates the table base address to indicate a location of the new table in the memory. When resizing the original table, the computing device updates the table size to indicate a new size.

Abstract: In one form, scheduling data migration comprises determining whether the data is likely to be used by an input/output (I/O) device, the data being at a location remote to the I/O device; and scheduling the data for migration from the remote location to a location local to the I/O device in response to determining that the data is likely to be used by the I/O device.

Abstract: An IOMMU for controlling requests by an I/O device to a system memory of a computer system includes control logic and a cache memory. The control logic may translate an address received in a request from the I/O device. If the request includes a transaction layer protocol (TLP) packet with a process address space identifier (PASID) prefix, the control logic may perform a two-level guest translation. Accordingly, the control logic may access a set of guest page tables to translate the address received in the request. A pointer in a last guest page table points to a first table in a set of nested page tables. The control logic may use the pointer in a last guest page table to access the set of nested page tables to obtain a system physical address (SPA) that corresponds to a physical page in the system memory. The cache memory stores completed translations.

Abstract: A computing device with a queue stored in a memory of the computing device is described. The queue may be relocated and/or resized in the memory using a queue address, a queue size, a head pointer, and/or a tail pointer associated with the queue. During operation, a processor, at the request of a software entity, updates one or more values associated with the queue to relocate and/or resize the queue. In response, a write mechanism performs one or more operations to enable the use of the relocated and/or resized queue. In addition, when the queue is relocated, the processor, at the request of the software entity, performs one or more operations to process remaining valid entries in an original location of the queue.

Abstract: In one form, scheduling data migration comprises determining whether the data is likely to be used by an input/output (I/O) device, the data being at a location remote to the I/O device; and scheduling the data for migration from the remote location to a location local to the I/O device in response to determining that the data is likely to be used by the I/O device.

Abstract: A virtual input/output memory management unit (IOMMU) is configured to provide a firewall around memory requests associated with an input/output (I/O) device. The virtual IOMMU uses data structures including a guest page table, a host page table and a general control register (i.e., GCR3) table. The guest page table is implemented in hardware to support the speed requirements of the virtual IOMMU. The GCR3 table is indexed using a virtual DeviceID parameter stored in a device table.

Abstract: In one form, a data processing system includes volatile and non-volatile memory, a central processing unit, and at least one peripheral device. The central processing unit executes a selected one of a plurality of software applications as directed by an operating system by transferring the selected software application from the non-volatile memory to the volatile memory and executing instructions associated with the selected software application from the volatile memory. The at least one peripheral device includes a real-time clock for defining execution contexts for the plurality of software applications. The data processing system further includes a usage pattern analyzer adapted to store history information associated with an execution context for each of the plurality of software applications, and to use the history information to direct the operating system to take at least one action based on the history information.

Abstract: Memory units and computer systems are provided. The computer systems include a memory unit. The memory unit includes a stable storage unit, an unstable storage unit, and a controller. The unstable storage unit stores pending write operations for the stable storage unit. The controller is configured to determine the locations in the unstable storage that store the pending write information and to selectively write the pending write operations to the stable storage unit when power to the memory unit is interrupted.

Abstract: Embodiments include methods, systems, and computer storage devices directed to identifying that a trusted boot mode (TBM) control bit is set in an input/output memory management unit (IOMMU) and configuring the IOMMU to block a DMA request received by the IOMMU from a peripheral in response to the identifying.

Abstract: A method for identifying and reporting interrupt behavior includes incrementing a counter when an interrupt signal is a designated type and is not received from an approved peripheral device, and performing a corrective action when the counter reaches a threshold value. In some embodiments, the designated type of the interrupt signal comprises a System Management Interrupt (SMI), which has the capability of halting operations at all processors within a system to execute associated instructions within a protected circumstance, resuming normal operations for each of the plurality of processors when the corrective action has been completed. In another embodiment, the corrective action includes creating a report identifying, within the same protected circumstance, the interrupt signal as an SMI. In some embodiments, the method performs a different corrective action when an interrupt signal is a designated type and is received from an approved peripheral device and decrements a counter.

Abstract: In a virtualized computer system without an IOMMU, all application IO requests must be processed by the guest operating system and by the hypervisor so that addresses are translated (twice) and validated (twice) properly. In a virtualized computer system with an IOMMU containing one “stage” of translation, the peripheral can safely be assigned directly to a guest OS because the IOMMU can be programmed to translate and check addresses issued by the device. As a result, route IO overhead due to hypervisor intervention can be eliminated. In one example, in a virtualized computer system with an IOMMU supporting two “stages” of translation, the peripheral can safely be assigned directly to an application within a guest OS. As a result, route IO overhead due to hypervisor and guest OS processing can be eliminated. This allows an application to achieve higher IO performance.

Abstract: A device may receive a direct memory access request that identifies a virtual address. The device may determine whether the virtual address is within a particular range of virtual addresses. The device may selectively perform a first action or a second action based on determining whether the virtual address is within the particular range of virtual addresses. The first action may include causing a first address translation algorithm to be performed to translate the virtual address to a physical address associated with a memory device when the virtual address is not within the particular range of virtual addresses. The second action may include causing a second address translation algorithm to be performed to translate the virtual address to the physical address when the virtual address is within the particular range of virtual addresses. The second address translation algorithm may be different from the first address translation algorithm.

Abstract: The described embodiments include a computing device with a queue stored in a memory of the computing device. In the described embodiments, the queue may be relocated and/or resized in the memory using a queue address, a queue size, a head pointer, and/or a tail pointer associated with the queue. In some embodiments, a processor, at the request of a software entity, updates one or more values associated with the queue to relocate and/or resize the queue. In response, a write mechanism performs one or more operations to enable the use of the relocated and/or resized queue. In addition, in some embodiments, the processor, at the request of the software entity, performs one or more operations to process remaining valid entries in an original location of the queue after the queue has been relocated.

Abstract: An input/output memory management unit (IOMMU) having an “invalidate all” command available to clear the contents of cache memory is presented. The cache memory provides fast access to address translation data that has been previously obtained by a process. A typical cache memory includes device tables, page tables and interrupt remapping entries. Cache memory data can become stale or be compromised from security breaches or malfunctioning devices. In these circumstances, a rapid approach to clearing cache memory content is provided.

Abstract: Embodiments of the present invention address deficiencies of the art in respect to trusted platform module (TPM) unification in a trusted computing environment and provide a novel and non-obvious method, system and computer program product for trusted platform module data harmonization. In one embodiment of the invention, a TPM log harmonization method can include designating both a single master TPM for a master node among multiple nodes, and also a multiplicity of subsidiary TPMs for remaining ones of the nodes. The method further can include extending the single master TPM with a measurement representing a rendezvous operation for the nodes.

Abstract: A method of managing peripherals is performed in a device coupled to a processor in a computer system. In the method, information associated with I/O activity for one or more peripherals is recorded in a first segment of a log. A second segment of the log is identified based on a next-segment pointer associated with the first segment of the log. In response to detecting a lack of available capacity in the first segment of the log, information associated with further I/O activity for the one or more peripherals is recorded in the second segment of the log.

Abstract: A method of managing peripherals is performed in a device coupled to a processor in a computer system. In the method, information associated with I/O activity for one or more peripherals is recorded in a first segment of a log. A second segment of the log is identified based on a next-segment pointer associated with the first segment of the log. In response to detecting a lack of available capacity in the first segment of the log, information associated with further I/O activity for the one or more peripherals is recorded in the second segment of the log.

Abstract: A computer system is provided for preventing peripheral devices and/or processor cores from accessing restricted portions of system memory. For example, the computer system can include a host bridge, system memory coupled to the host bridge via a first access bus, a security processor coupled to the host bridge via a memory access bus that allows the security processor to access system memory and to access the peripheral device, and a security processor memory management unit (SPMMU) coupled between the peripheral device and the host bridge. The security processor is configured to program the SPMMU via the memory access bus to specify a first restricted range of physical addresses in the system memory that the peripheral device is not permitted to access. The SPMMU can then process access requests from the peripheral device and deny access requests that are determined to be within the first restricted range.

Abstract: A system for processing interrupts in a virtualized computing environment includes a virtual interrupt controller to provide virtual interrupts from peripherals to virtual machines. The system also includes a virtual interrupt filter that has an estimator circuit to provide an estimate of what proportion of interrupts from one or more of the peripherals are virtual interrupts. A determination is made as to whether the estimate satisfies a criterion; if it does, incoming interrupts are blocked.