Abstract: A signal converter for converting a bi-phase-level data stream to non-ret-to-zero-level data. The bi-phase-level data stream is input to a detector circuit. When the detector circuit detects a high level for more than half of a bit period, the detector circuit provides a logic zero pulse at a state S7. If the high level is not at the logic one state for a sufficient time period the detector circuit will not reach state s7. If the time period is to short than the detector circuit is reset to state s0. This high level pulse occurs whenever the second half of a bit period is high followed by a high in the first half of the following bit period. A sample is taken on the first half of every bit period. A low at the detector circuit keeps the detector circuit at state s0. A clock signal generating circuit receives the logic zero pulse and then proceeds through its states s0-s10. When state S1 is reached a clock pulse is provided by the clock signal generating circuit.

Abstract: An interface circuit which receives a PCM telemetry data stream comprising waveform divided into 100 words including a three word frame sync signal. The PCM data stream is supplied to a comparator which converts input telemetry signal to a TTL compatible signal. When the PCM data is unencrypted, the PCM data stream is supplied to a de-randomizer circuit which de-randomizes the randomized data. A bit sync circuit which also receives the PCM data stream generates a 320 kHz clock signal which is synchronized to the incoming PCM data stream. The de-randomized PCM telemetry data stream which is in a serial format and the 320 kHz clock signal pass through a digital multiplexer to a universal synchronous asynchronous receiver transmitter. When the receiver transmitter detects a PCM frame sync signal for a frame of PCM data, it interrupts a master microprocessor which then retrieves each word of PCM data from the frame. The master microprocessor writes the frame of PCM data into one bank of a dual Port RAM.

Abstract: An electronics circuit for frequency shift keying a continuous-running caer, such as a sinewave, which allows the user to vary two closely spaced frequencies from a personal computer. The electronics circuit of the present invention comprises a microcontroller which has stored therein a lower frequency and an offset frequency. After the electronics circuit is powered up the microcontroller enters the MAIN program and generates control and address signals to effect a transfer of thirty two data bits representing the lower frequency from the microcontroller to a pair of eight bit RAMS. A programmed array logic device, which receives addresses from the microcontroller, decodes the addresses and then provides chip select and output enable signals to the RAMs to allow the thirty two data bits to be written into the RAMs with the write signal being provided by the microcontroller.

Abstract: An interface circuit for receiving an analog PAM telemetry data stream from missile's telemetry unit. The PAM data stream comprises a waveform divided into 64 channels and includes a sync signal. The PAM data stream is supplied to a filter which removes from the PAM data stream subcarrier channel oscillator frequencies. The filtered data stream is next supplied to an analog-to-digital converter which converts each sample of the data stream to an equivalent twelve bit PAM data word which is supplied to a slave microprocessor. The slave microprocessor processes each of the sixty four PAM channels by utilizing a 25.6 kHz PAM clock signal generated by a PAM signal processing circuit. The slave microprocessor first checks for the sync signal. When the sync signal is decoded, the slave microprocessor sends a message to a master microprocessor via a dual port RAM indicating that the sync signal was located. The master microprocessor will respond with an acknowledgement message to the slave microprocessor.

Abstract: A digital circuit comprising a pair of D Flip-Flops which synchronize an oming NRZ.sub.-- L serial data stream to an external ten megahertz clock signal. The combination of a third D Flip-Flop and an EXCLUSIVE-NOR gate generates a clear pulse whenever a change of state occurs within the synchronized serial data stream. This clear pulse is supplied to a ten state state machine resetting the state machine to state S0. When the state machine transition to state S4 the state machine generates an enable signal which is supplied to a toggle Flip-Flop enabling the Flip-Flop allowing the Flip-Flop to change state. The ten megahertz clock signal then clocks the toggle Flip-Flop causing the Flip-Flop to change state. At state S9 the state machine again provides an enable signal to the toggle Flip-Flop enabling the toggle Flip-Flop which allows the ten megahertz clock signal to change the state of the output of the toggle Flip-Flop.

Abstract: A Gray code counter is provided having identical modular circuits with each odular circuit providing a Gray code count sequence having a predetermined number of bits and an enable signal to enable a successive modular circuit of the Gray code counter. Each modular circuit of the Gray code counter enables a successive modular circuit only during certain predetermined counts of the Gray code count sequence. The number of modules required to implement the counter is determined by the number of binary bits per module and the total number of binary bits provided by the counter. The Gray code counter can operate either in an up mode count or a down mode count in accordance with the Gray code count sequence.