Patents by Inventor Andrew Herdrich
Andrew Herdrich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230315632Abstract: Techniques and mechanisms to facilitate access to a cache based on a dual basis partition scheme. In an embodiment, a first one or more registers of a processor provide information which describes multiple set-wise partitions of a cache. A second one or more registers of the processor provides additional information which describes multiple way-wise partitions of the cache. A virtual cache is defined as that region of the cache which is both in a particular set-wise partition, and in a particular way-wise partition. In another embodiment, a cache agent of the processor performs operations, based on the set-wise partitioning and the way-wise partitioning, to determine a mapping of one address—which is provided in a memory access request, and which indicates a location in one virtual cache—to another address which indicates another location in a different virtual cache.Type: ApplicationFiled: April 1, 2022Publication date: October 5, 2023Applicant: Intel CorporationInventors: Philip Abraham, Stephen Van Doren, Ritu Gupta, Andrew Herdrich
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Patent number: 11531562Abstract: Systems, methods, and apparatuses for resource monitoring identification reuse are described. In an embodiment, a system comprising a hardware processor core to execute instructions storage for a resource monitoring identification (RMID) recycling instructions to be executed by a hardware processor core, a logical processor to execute on the hardware processor core, the logical processor including associated storage for a RMID and state, are described.Type: GrantFiled: October 22, 2020Date of Patent: December 20, 2022Assignee: Intel CorporationInventors: Matthew Fleming, Edwin Verplanke, Andrew Herdrich, Ravishankar Iyer
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Patent number: 11515890Abstract: Technologies for applying a redundancy encoding scheme to segmented portions of a data block include an endpoint computing device communicatively coupled to a destination computing device. The endpoint computing device is configured to divide a block of data into a plurality of data segments as a function of a transmit window size and a redundancy encoding scheme, and generate redundant data usable to reconstruct each of the plurality of data segments. The endpoint computing device is additionally configured to format a series of network packets that each includes a data segment of the plurality of data segments and generated redundant data for at least one other data segment of the plurality of data segments. Further, the endpoint computing device is configured to transport each of the series of network packets to a destination computing device. Other embodiments are described herein.Type: GrantFiled: September 30, 2021Date of Patent: November 29, 2022Assignee: Intel CorporationInventors: Patrick Connor, Kapil Sood, Scott Dubal, Andrew Herdrich, James Hearn
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Publication number: 20220103185Abstract: Technologies for applying a redundancy encoding scheme to segmented portions of a data block include an endpoint computing device communicatively coupled to a destination computing device. The endpoint computing device is configured to divide a block of data into a plurality of data segments as a function of a transmit window size and a redundancy encoding scheme, and generate redundant data usable to reconstruct each of the plurality of data segments. The endpoint computing device is additionally configured to format a series of network packets that each includes a data segment of the plurality of data segments and generated redundant data for at least one other data segment of the plurality of data segments. Further, the endpoint computing device is configured to transport each of the series of network packets to a destination computing device. Other embodiments are described herein.Type: ApplicationFiled: September 30, 2021Publication date: March 31, 2022Inventors: Patrick Connor, Kapil Sood, Scott Dubal, Andrew Herdrich, James Hearn
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Publication number: 20220100247Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.Type: ApplicationFiled: September 26, 2020Publication date: March 31, 2022Applicant: Intel CorporationInventors: Vivek Garg, Ankush Varma, Krishnakanth Sistla, Nikhil Gupta, Nikethan Shivanand Baligar, Stephen Wang, Nilanjan Palit, Timothy Kam, Adwait Purandare, Ujjwal Gupta, Stanley Chen, Dorit Shapira, Shruthi Venugopal, Suresh Chemudupati, Rupal Parikh, Eric Dehaemer, Pavithra Sampath, Phani Kumar Kandula, Yogesh Bansal, Dean Mulla, Michael Tulanowski, Stephen Haake, Andrew Herdrich, Ripan Das
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Publication number: 20210406147Abstract: An apparatus and method for closed loop dynamic resource allocation.Type: ApplicationFiled: June 27, 2020Publication date: December 30, 2021Inventors: BIN LI, REN WANG, KSHITIJ ARUN DOSHI, FRANCESC GUIM BERNAT, YIPENG WANG, RAVISHANKAR IYER, ANDREW HERDRICH, TSUNG-YUAN TAI, ZHU ZHOU, RASIKA SUBRAMANIAN
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Publication number: 20210374848Abstract: Systems, methods, and apparatuses for resource bandwidth monitoring and control are described. For example, in some embodiments, an apparatus comprising a requestor device to send a credit based request, a receiver device to receive and consume the credit based request, and a delay element in a return path between the requestor and receiver devices, the delay element to delay a credit based response from the receiver to the requestor are detailed.Type: ApplicationFiled: August 13, 2021Publication date: December 2, 2021Inventors: Andrew HERDRICH, Edwin VERPLANKE, Ravishankar IYER, Christopher GIANOS, Jeffrey D. CHAMBERLAIN, Ronak SINGH, Julius MANDELBLAT, Bret Toll
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Patent number: 11146288Abstract: Technologies for applying a redundancy encoding scheme to segmented portions of a data block include an endpoint computing device communicatively coupled to a destination computing device. The endpoint computing device is configured to divide a block of data into a plurality of data segments as a function of a transmit window size and a redundancy encoding scheme, and generate redundant data usable to reconstruct each of the plurality of data segments. The endpoint computing device is additionally configured to format a series of network packets that each includes a data segment of the plurality of data segments and generated redundant data for at least one other data segment of the plurality of data segments. Further, the endpoint computing device is configured to transport each of the series of network packets to a destination computing device. Other embodiments are described herein.Type: GrantFiled: March 11, 2020Date of Patent: October 12, 2021Assignee: Intel CorporationInventors: Patrick Connor, Kapil Sood, Scott Dubal, Andrew Herdrich, James Hearn
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Patent number: 11121940Abstract: Examples include techniques to meet quality of service (QoS) requirements for a fabric point to point connection. Examples include an application hosted by a compute node coupled with a fabric requesting bandwidth for a point to point connection through the fabric and the request being granted or not granted based at least partially on whether bandwidth is available for allocation to meet one or more QoS requirements.Type: GrantFiled: March 27, 2017Date of Patent: September 14, 2021Assignee: Intel CorporationInventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Andrew Herdrich, Edwin Verplanke
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Publication number: 20210232426Abstract: A simultaneous multi-threading (SMT) processor core capable of thread-based biasing with respect to execution resources. The SMT processor includes priority controller circuitry to determine a thread priority value for each of a plurality of threads to be executed by the SMT processor core and to generate a priority vector comprising the thread priority value of each of the plurality of threads. The SMT processor further includes thread selector circuitry to make execution cycle assignments of a pipeline by assigning to each of the plurality of threads a portion of the pipeline's execution cycles based on each thread's priority value in the priority vector. The thread selector circuitry is further to select, from the plurality of threads, tasks to be processed by the pipeline based on the execution cycle assignments.Type: ApplicationFiled: November 10, 2020Publication date: July 29, 2021Applicant: Intel CorporationInventors: Andrew Herdrich, Ian Steiner, Leeor Peled, Michael Prinke, Eylon Toledano
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Patent number: 10929323Abstract: Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.Type: GrantFiled: October 14, 2019Date of Patent: February 23, 2021Assignee: Intel CorporationInventors: Ren Wang, Yipeng Wang, Andrew Herdrich, Jr-Shian Tsai, Tsung-Yuan C. Tai, Niall D. McDonnell, Hugh Wilkinson, Bradley A. Burres, Bruce Richardson, Namakkal N. Venkatesan, Debra Bernstein, Edwin Verplanke, Stephen R. Van Doren, An Yan, Andrew Cunningham, David Sonnier, Gage Eads, James T. Clee, Jamison D. Whitesell, Jerry Pirog, Jonathan Kenny, Joseph R. Hasting, Narender Vangati, Stephen Miller, Te K. Ma, William Burroughs
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Publication number: 20210042254Abstract: Methods and apparatus for an accelerator controller hub (ACH). The ACH may be a stand-alone component or integrated on-die or on package in an accelerator such as a GPU. The ACH may include a host device link (HDL) interface, one or more Peripheral Component Interconnect Express (PCIe) interfaces, one or more high performance accelerator link (HPAL) interfaces, and a router, operatively coupled to each of the HDL interface, the one or more PCIe interfaces, and the one or more HPAL interfaces. The HDL interface is configured to be coupled to a host CPU via an HDL link and the one or more HPAL interfaces are configured to be coupled to one or more HPALs that are used to access high performance accelerator fabrics (HPAFs) such as NVlink fabrics and CCIX (Cache Coherent Interconnect for Accelerators) fabrics. Platforms including ACHs or accelerators with integrated ACHs support RDMA transfers using RDMA semantics to enable transfers between accelerator memory on initiators and targets without CPU involvement.Type: ApplicationFiled: October 28, 2020Publication date: February 11, 2021Inventors: Pratik Marolia, Andrew Herdrich, Rajesh Sankaran, Rahul Pal, David Puffer, Sayantan Sur, Ajaya Durg
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Publication number: 20210042146Abstract: Systems, methods, and apparatuses for resource monitoring identification reuse are described. In an embodiment, a system comprising a hardware processor core to execute instructions storage for a resource monitoring identification (RMID) recycling instructions to be executed by a hardware processor core, a logical processor to execute on the hardware processor core, the logical processor including associated storage for a RMID and state, are described.Type: ApplicationFiled: October 22, 2020Publication date: February 11, 2021Inventors: Matthew FLEMING, Edwin VERPLANKE, Andrew HERDRICH, Ravishankar IYER
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Patent number: 10866834Abstract: A simultaneous multi-threading (SMT) processor core capable of thread-based biasing with respect to execution resources. The SMT processor includes priority controller circuitry to determine a thread priority value for each of a plurality of threads to be executed by the SMT processor core and to generate a priority vector comprising the thread priority value of each of the plurality of threads. The SMT processor further includes thread selector circuitry to make execution cycle assignments of a pipeline by assigning to each of the plurality of threads a portion of the pipeline's execution cycles based on each thread's priority value in the priority vector. The thread selector circuitry is further to select, from the plurality of threads, tasks to be processed by the pipeline based on the execution cycle assignments.Type: GrantFiled: March 29, 2019Date of Patent: December 15, 2020Assignee: Intel CorporationInventors: Andrew Herdrich, Ian Steiner, Leeor Peled, Michael Prinke, Eylon Toledano
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Publication number: 20200310865Abstract: A simultaneous multi-threading (SMT) processor core capable of thread-based biasing with respect to execution resources. The SMT processor includes priority controller circuitry to determine a thread priority value for each of a plurality of threads to be executed by the SMT processor core and to generate a priority vector comprising the thread priority value of each of the plurality of threads. The SMT processor further includes thread selector circuitry to make execution cycle assignments of a pipeline by assigning to each of the plurality of threads a portion of the pipeline's execution cycles based on each thread's priority value in the priority vector. The thread selector circuitry is further to select, from the plurality of threads, tasks to be processed by the pipeline based on the execution cycle assignments.Type: ApplicationFiled: March 29, 2019Publication date: October 1, 2020Applicant: Intel CorporationInventors: Andrew Herdrich, Ian Steiner, Leeor Peled, Michael Prinke, Eylon Toledano
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Publication number: 20200280324Abstract: Technologies for applying a redundancy encoding scheme to segmented portions of a data block include an endpoint computing device communicatively coupled to a destination computing device. The endpoint computing device is configured to divide a block of data into a plurality of data segments as a function of a transmit window size and a redundancy encoding scheme, and generate redundant data usable to reconstruct each of the plurality of data segments. The endpoint computing device is additionally configured to format a series of network packets that each includes a data segment of the plurality of data segments and generated redundant data for at least one other data segment of the plurality of data segments. Further, the endpoint computing device is configured to transport each of the series of network packets to a destination computing device. Other embodiments are described herein.Type: ApplicationFiled: March 11, 2020Publication date: September 3, 2020Inventors: Patrick Connor, Kapil Sood, Scott Dubal, Andrew Herdrich, James Hearn
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Patent number: 10630315Abstract: Technologies for applying a redundancy encoding scheme to segmented portions of a data block include an endpoint computing device communicatively coupled to a destination computing device. The endpoint computing device is configured to divide a block of data into a plurality of data segments as a function of a transmit window size and a redundancy encoding scheme, and generate redundant data usable to reconstruct each of the plurality of data segments. The endpoint computing device is additionally configured to format a series of network packets that each includes a data segment of the plurality of data segments and generated redundant data for at least one other data segment of the plurality of data segments. Further, the endpoint computing device is configured to transport each of the series of network packets to a destination computing device. Other embodiments are described herein.Type: GrantFiled: September 29, 2017Date of Patent: April 21, 2020Assignee: Intel CorporationInventors: Patrick Connor, Kapil Sood, Scott Dubal, Andrew Herdrich, James Hearn
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Patent number: 10613876Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.Type: GrantFiled: June 22, 2017Date of Patent: April 7, 2020Assignee: Intel CorporationInventors: Andrew Herdrich, Ramesh Illikkal, Donald Newell, Ravishankar Iyer, Vineet Chadha
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SYSTEM, METHOD, AND APPARATUS FOR SNAPSHOT PREFETCHING TO IMPROVE PERFORMANCE OF SNAPSHOT OPERATIONS
Publication number: 20200104259Abstract: A snapshot prefetcher to perform snapshot prefetching to improve performance of snapshot read operations. An apparatus embodiment includes a snapshot read tracking circuitry to track snapshot read requests made by a first processor core to read a plurality of cache lines, and to detect a snapshot read access stream based on the tracked snapshot read requests. A snapshot prefetch issuing circuitry of the apparatus to issue, based on the detected snapshot read access stream, one or more snapshot prefetch requests, including a first snapshot prefetch request to prefetch data from a first cache line stored in, and owned exclusively by, a first storage location outside the first processor core. The snapshot prefetch issuing circuitry further to store the prefetched data in a second storage location within the first processor core, wherein after the prefetch, exclusive ownership of the first cache line is to remain with the first storage location.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Inventors: Ren Wang, Lawrence C. Stewart, Binh Pham, Andrew Herdrich, Venkata Krishnan, Anil Vasudevan, Joseph Nuzman, Tsung-Yuan Tai -
Publication number: 20200042479Abstract: Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.Type: ApplicationFiled: October 14, 2019Publication date: February 6, 2020Applicant: Intel CorporationInventors: Ren Wang, Yipeng Wang, Andrew Herdrich, Jr-Shian Tsai, Tsung-Yuan C. Tai, Niall D. McDonnell, Hugh Wilkinson, Bradley A. Burres, Bruce Richardson, Namakkal N. Venkatesan, Debra Bernstein, Edwin Verplanke, Stephen R. Van Doren, An Yan, Andrew Cunningham, David Sonnier, Gage Eads, James T. Clee, Jamison D. Whitesell, Jerry Pirog, Jonathan Kenny, Joseph R. Hasting, Narender Vangati, Stephen Miller, Te K. Ma, William Burroughs