Patents by Inventor Andrew J. RUSHING

Andrew J. RUSHING has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Opportunistic cache injection of data into lower latency levels of the cache hierarchy
    Patent number: 10216640
    Abstract: According to one general aspect, a method may include receiving a request, from a non-central processor device that is configured to perform a direct memory access, to write data within a memory system at a memory address. The method may also include determining if a cache tag hit is generated, based upon the memory address, by a caching tier of the memory system that is closer, latency-wise, to a central processor than a coherent memory interconnect. The method may further include if the caching tier generated the cache tag hit, injecting the data into the caching tier.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: February 26, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Andrew J. Rushing, Kevin M. Lepak
  • OPPORTUNISTIC CACHE INJECTION OF DATA INTO LOWER LATENCY LEVELS OF THE CACHE HIERARCHY
    Publication number: 20150269084
    Abstract: According to one general aspect, a method may include receiving a request, from a non-central processor device that is configured to perform a direct memory access, to write data within a memory system at a memory address. The method may also include determining if a cache tag hit is generated, based upon the memory address, by a caching tier of the memory system that is closer, latency-wise, to a central processor than a coherent memory interconnect. The method may further include if the caching tier generated the cache tag hit, injecting the data into the caching tier.
    Type: Application
    Filed: March 9, 2015
    Publication date: September 24, 2015
    Inventors: Andrew J. RUSHING, Kevin M. LEPAK