Patents by Inventor Andrew J. Walker

Andrew J. Walker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080315294
    Abstract: A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness such that a sensitivity parameter relating an electrical interaction between the gate electrodes of the access device and the memory device is less than a predetermined value. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings.
    Type: Application
    Filed: June 19, 2008
    Publication date: December 25, 2008
    Inventor: Andrew J. Walker
  • Patent number: 7462521
    Abstract: A dual-gate device is formed over and insulated from a semiconductor substrate which may include additional functional circuits that can be interconnected to the dual-gate device. The dual-gate device includes two semiconductor devices formed on opposite surfaces of a common active semiconductor region which is provided a thickness and material sufficient to isolate the semiconductor devices from electrostatically interacting. In one embodiment, one of the semiconductor devices includes a charge storing layer, such as an ONO layer. Such a dual-gate device is suitable for use in a non-volatile memory array.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: December 9, 2008
    Inventors: Andrew J. Walker, Maitreyee Mahajani
  • Patent number: 7459755
    Abstract: A scalable semiconductor device is formed using control gates formed on opposite sides of a semiconductor layer. A first control gate is formed electrically isolated from a first surface of the semiconductor layer by a first dielectric layer, such that, when a first voltage is applied on the first control gate, a first depletion region is formed in the semiconductor layer opposite the first control gate. A second control gate and a third control gate are also formed, each isolated from the semiconductor region by a second dielectric layer formed on a second surface of the semiconductor layer opposite the first surface.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: December 2, 2008
    Inventor: Andrew J. Walker
  • Publication number: 20080283921
    Abstract: A dual-gate device includes an active layer between a first gate structure and a second gate structure. Each gate structure is isolated from the active layer by a dielectric layer and is located above a semiconductor or channel region in the active layer defined by spaced-apart diffusion regions formed by implanting antimony ions. The antimony-doped diffusion regions are particularly suitable in the dual-gate device because it can be implanted and activated at a temperature less than 900° C. and show little movement of the implanted antimony ions even after numerous thermal steps in the manufacturing process. As a result, dual-gate devices with well-controlled channel lengths may be achieved.
    Type: Application
    Filed: May 15, 2007
    Publication date: November 20, 2008
    Inventor: Andrew J. Walker
  • Publication number: 20080283901
    Abstract: A dual-gate memory cell includes a first memory device and a second memory device each having a gate electrode and a charge storage gate dielectric layer. The first and second memory devices share a channel region and source and drain regions. Such a memory cell is read by sensing the charge in one of the dielectric layers by applying a first voltage in the gate electrode associated with the dielectric layer sensed, and applying a second voltage substantially different than the first voltage in the other dielectric layer.
    Type: Application
    Filed: May 15, 2007
    Publication date: November 20, 2008
    Inventor: Andrew J. Walker
  • Publication number: 20080286925
    Abstract: The present invention provides a non-volatile memory string having serially connected dual-gate devices, in which a first gate dielectric layer adjacent a first gate electrode layer in each dual-gate device is charge-storing and in which the second gate electrode adjacent a non-charge storing gate dielectric layer are connected in common. In one implementation, the second gate electrodes of the dual-gate devices in the memory string are provided by a continuous layer of doped polysilicon, tungsten, tantalum nitride, tungsten nitride or any combination of two or more of these conductors.
    Type: Application
    Filed: May 27, 2008
    Publication date: November 20, 2008
    Inventor: Andrew J. Walker
  • Publication number: 20080285349
    Abstract: The present invention provides a non-volatile memory string having serially connected dual-gate devices, in which a first gate dielectric layer adjacent a first gate electrode layer in each dual-gate device is charge-storing and in which the second gate electrode adjacent a non-charge storing gate dielectric layer are connected in common. In one implementation, the second gate electrodes of the dual-gate devices in the memory string are provided by a continuous layer of doped polysilicon, tungsten, tantalum nitride, tungsten nitride or any combination of two or more of these conductors.
    Type: Application
    Filed: May 15, 2007
    Publication date: November 20, 2008
    Inventor: Andrew J. Walker
  • Patent number: 7433233
    Abstract: An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: October 7, 2008
    Assignee: SanDisk 3D LLC
    Inventors: En-Hsing Chen, Andrew J. Walker, Roy E. Scheuerlein, Sucheta Nallamothu, Alper Ilkbahar, Luca G. Fasoli
  • Patent number: 7410845
    Abstract: A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness, such that when a pass voltage is applied to the gate electrode of the access device, the access device and the memory device remains isolated, such that the charge stored in the memory device is unaffected by the pass voltage. The pass voltage is determined from a range of voltages, when applied to the access device, has no effect on the threshold voltage of the memory device. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: August 12, 2008
    Inventor: Andrew J. Walker
  • Publication number: 20080083943
    Abstract: A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness such that electrical interaction between the access device and the memory device is characterized by a sensitivity parameter having a value within a predetermined range for a sub-threshold voltage applied to a gate electrode of the access device. To achieve good scalability of the dual-gate memory cells, the semiconductor layer between the memory device gate and access device gate can be thinned. This results in a larger sensitivity parameter but this parameter is still small enough to avoid memory charge disturbs. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings.
    Type: Application
    Filed: May 15, 2007
    Publication date: April 10, 2008
    Inventor: Andrew J. Walker
  • Publication number: 20080084745
    Abstract: A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness such that a sensitivity parameter relating an electrical interaction between the gate electrodes of the access device and the memory device is less than a predetermined value. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings.
    Type: Application
    Filed: October 10, 2006
    Publication date: April 10, 2008
    Inventor: Andrew J. Walker
  • Patent number: 7339821
    Abstract: A memory circuit and a method is provided for programming a dual-gate memory cell without program disturb in other dual-gate memory cells in the memory circuit coupled by common word lines. In one embodiment, the method uses a self-boosting technique on unselected memory cells having source and drain regions in the shared semiconductor layer between their memory devices and their access devices brought to a predetermined voltage close to the threshold voltage of their access devices, thereby rendering the source and drain regions substantially floating. In some embodiments, the source and drain regions are brought to the predetermined voltage via one or more select gates and intervening access gates. In some embodiments, the select gates are overdriven.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: March 4, 2008
    Assignee: Schiltron Corporation
    Inventor: Andrew J. Walker
  • Publication number: 20070284621
    Abstract: A scalable semiconductor device is formed using control gates formed on opposite sides of a semiconductor layer. A first control gate is formed electrically isolated from a first surface of the semiconductor layer by a first dielectric layer, such that, when a first voltage is applied on the first control gate, a first depletion region is formed in the semiconductor layer opposite the first control gate. A second control gate and a third control gate are also formed, each isolated from the semiconductor region by a second dielectric layer formed on a second surface of the semiconductor layer opposite the first surface.
    Type: Application
    Filed: May 25, 2006
    Publication date: December 13, 2007
    Inventor: Andrew J. Walker
  • Patent number: 7250646
    Abstract: There is provided a monolithic three dimensional TFT mask ROM array. The array includes a plurality of device levels. Each of the plurality of device levels contains a first set of enabled TFTs and a second set of partially or totally disabled TFTs.
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: July 31, 2007
    Assignee: Sandisk 3D, LLC.
    Inventors: Andrew J. Walker, Christopher Petti
  • Patent number: 7233522
    Abstract: An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: June 19, 2007
    Assignee: SanDisk 3D LLC
    Inventors: En-Hsing Chen, Andrew J. Walker, Roy E. Scheuerlein, Sucheta Nallamothu, Alper Ilkbahar, Luca G. Fasoli
  • Patent number: 7224013
    Abstract: The invention provides for a junction diode including a heavily doped first region having a first conductivity type, a second lightly doped or intrinsic region having a second conductivity type, and a third heavily doped region having a second conductivity type. The junction diode comprises more than one semiconductor or semiconductor alloy. In preferred embodiments, the lightly doped or intrinsic region has a higher proportion of germanium than on or the other or both of the heavily doped regions. In preferred embodiments, the junction diode is vertically oriented, and the top region has a higher proportion of silicon than the other regions.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: May 29, 2007
    Assignee: Sandisk 3D LLC
    Inventors: S. Brad Herner, Andrew J. Walker
  • Patent number: 7221588
    Abstract: An exemplary NAND string memory array includes at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, and NAND strings including a series select device at each end thereof. Another exemplary NAND string memory array includes a group of more than four adjacent NAND strings within the same memory block each associated with a respective global bit line not shared by the other NAND string of the group. Another exemplary NAND string memory array includes NAND strings on identical pitch as their respective global bit lines.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: May 22, 2007
    Assignee: Sandisk 3D LLC
    Inventors: Luca G. Fasoli, Roy E. Scheuerlein, En-Hsing Chen, Sucheta Nallamothu, Maitreyee Mahajani, Andrew J. Walker
  • Patent number: 7132335
    Abstract: An array of transistors includes a plurality of transistors, a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction. Each transistor includes a source, a drain, a channel and a localized charge storage dielectric. A first transistor of the plurality of transistors and a second transistor of the plurality of transistors share a common source/drain. A first localized charge storage dielectric of the first transistor does not overlap the common source/drain and a second localized charge storage dielectric of the second transistor overlaps the common source/drain.
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: November 7, 2006
    Assignee: Sandisk 3D LLC
    Inventors: Alper Ilkbahar, Roy Scheuerlein, Andrew J. Walker, Luca Fasoli
  • Patent number: 7129538
    Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
    Type: Grant
    Filed: May 10, 2004
    Date of Patent: October 31, 2006
    Assignee: Sandisk 3D LLC
    Inventors: Thomas H. Lee, Vivek Subramanian, James M. Cleeves, Andrew J. Walker, Christopher Petti, Igor G. Kouznetzov, Mark G. Johnson, Paul M. Farmwald, Brad Herner
  • Patent number: 7023739
    Abstract: An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: April 4, 2006
    Assignee: Matrix Semiconductor, Inc.
    Inventors: En-Hsing Chen, Andrew J. Walker, Roy E. Scheuerlein, Sucheta Nallamothu, Alper Ilkbahar, Luca G. Fasoli