Patents by Inventor Andrew K. Chan

Andrew K. Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11441512
    Abstract: A cooling system for a cylinder head of an internal combustion engine includes a cylindrical seat configured to engage an exhaust valve, a first coolant jacket, and a first conduit. The exhaust valve seat defines an annular cooling passage extending along a circumference of the cylindrical seat. A wall of the cylindrical seat defines a first opening into the annular cooling passage and a second opening into the annular cooling passage, where the first opening is positioned diametrically opposite to the second opening. The first coolant jacket is positioned adjacent to a fire-deck of the internal combustion engine. The first conduit fluidly couples the first coolant jacket to the at least one of the first opening and the second opening to the annular cooling passage in the exhaust valve seat.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: September 13, 2022
    Assignee: Cummins Inc.
    Inventors: Andrew P. Perr, Robin J. Bremmer, Philipe F. Saad, Akintomide K. Akinola, Rick Vaughan Lewis, Jr., Dennis King Chan
  • Patent number: 11373222
    Abstract: Systems and methods electronically obtain data regarding a plurality of sources and corresponding amounts of resources received from the sources for a plurality of relationship instances each associated with one or more respective domains of a plurality of domains. For each relationship instance of the plurality of relationship instances: the system electronically identifies a rate to calculate an amount of resource due to one or more respective domains associated with the relationship instance based on a source of a resource received for the relationship instance and the one or more respective domains and calculates an amount of resources due to at least one respective domain associated with the relationship instance based on the identified rate. For each domain of the plurality of domains, the system aggregates a total amount of resources due to the domain based on the calculated amount of resources due for each relationship instance associated with the domain.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: June 28, 2022
    Assignee: Avalara, Inc.
    Inventors: Andrew Brandon Chan, Danielle Lear, Brian K. Mason, Andrew Z. Fountain, Patrick Collins Chesser, Patrick J. Hampton, David A. Goldstein
  • Patent number: 7830449
    Abstract: A display processor integrated circuit includes a display processor portion and an on-chip programmable logic portion. The programmable logic portion can be configured to implement custom video and/or image enhancement functions. The display processor portion performs block-based motion detection. If no motion is detected for a given block of pixels, then interline gaps in the block are filled using temporal interpolation. If motion is detected, then interline gaps are filled using spatial interpolation. To maintain accuracy without unduly increasing computational complexity, a less complex high angle spatial interpolation method is employed where a low angle tilt condition is not detected. A more computationally intensive low angle spatial interpolation method can therefore be employed in low angle tilt conditions. Integrated circuit cost is reduced by employing pipelining to write parts of segment buffers at the same time that other parts are being read to perform the interpolation process.
    Type: Grant
    Filed: April 3, 2007
    Date of Patent: November 9, 2010
    Inventors: Qinggang Zhou, Clyde H. Nagakura, Sheng-Fu Wu, Andrew K. Chan
  • Patent number: 7782398
    Abstract: A display processor integrated circuit (for example, for a television or for a digital camera) includes a display processor portion and an on-chip programmable logic portion. The on-chip programmable logic portion can be configured or programmed to implement custom video and/or image enhancement functions. Accordingly, an individual television or camera manufacturer can have his/her own custom enhancement function incorporated into the display processor integrated circuit by having the programmable logic portion configured or programmed appropriately. In one embodiment, the programming of the programmable logic portion involves changing just one mask, thereby reducing the cost, complexity and time associated with implementing the custom video/image enhancement function.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: August 24, 2010
    Inventors: Thomas M. Chan, Harry J. Raftopoulos, Andrew K. Chan
  • Patent number: 7346876
    Abstract: A method is disclosed whereby an inexpensive integrated circuit is provided for use in high volume electronic consumer devices of different makes, wherein each different make must perform a different special function. A common function required in all the different makes is realized in a substantially non-customizable portion. A dense mask-programmable portion is provided for realizing a special function. Interface circuitry is provided that enables an external FPGA to perform the special function at system operating speeds during system development. After system development, the circuitry implemented in the external FPGA is technology-mapped to the mask-programmable portion. A single mask is fashioned such that versions of the integrated circuit are produced with their mask-programmable portions customized to perform the special function.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: March 18, 2008
    Inventors: Andrew K. Chan, Thomas M. Chan, Po Weng Chiu
  • Patent number: 7218355
    Abstract: A display processor integrated circuit includes a display processor portion and an on-chip programmable logic portion. The programmable logic portion can be configured to implement custom video and/or image enhancement functions. The display processor portion performs block-based motion detection. If no motion is detected for a given block of pixels, then interline gaps in the block are filled using temporal interpolation. If motion is detected, then interline gaps are filled using spatial interpolation. To maintain accuracy without unduly increasing computational complexity, a less complex high angle spatial interpolation method is employed where a low angle tilt condition is not detected. A more computationally intensive low angle spatial interpolation method can therefore be employed in low angle tilt conditions. Integrated circuit cost is reduced by employing pipelining to write parts of segment buffers at the same time that other parts are being read to perform the interpolation process.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: May 15, 2007
    Inventors: Qinggang Zhou, Clyde H. Nagakura, Sheng-Fu Wu, Andrew K. Chan
  • Patent number: 7202908
    Abstract: A display processor integrated circuit includes a display processor portion and an on-chip programmable logic portion. The programmable logic portion can be configured to implement custom video and/or image enhancement functions. The display processor portion performs block-based motion detection. If no motion is detected for a given block of pixels, then interline gaps in the block are filled using temporal interpolation. If motion is detected, then interline gaps are filled using spatial interpolation. To maintain accuracy without unduly increasing computational complexity, a less complex high angle spatial interpolation method is employed where a low angle tilt condition is not detected. A more computationally intensive low angle spatial interpolation method can therefore be employed in low angle tilt conditions. Integrated circuit cost is reduced by employing pipelining to write parts of segment buffers at the same time that other parts are being read to perform the interpolation process.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: April 10, 2007
    Inventors: Qinggang Zhou, Clyde H. Nagakura, Sheng-Fu Wu, Andrew K. Chan
  • Publication number: 20040160526
    Abstract: A display processor integrated circuit includes a display processor portion and an on-chip programmable logic portion. The programmable logic portion can be configured to implement custom video and/or image enhancement functions. The display processor portion performs block-based motion detection. If no motion is detected for a given block of pixels, then interline gaps in the block are filled using temporal interpolation. If motion is detected, then interline gaps are filled using spatial interpolation. To maintain accuracy without unduly increasing computational complexity, a less complex high angle spatial interpolation method is employed where a low angle tilt condition is not detected. A more computationally intensive low angle spatial interpolation method can therefore be employed in low angle tilt conditions. Integrated circuit cost is reduced by employing pipelining to write parts of segment buffers at the same time that other parts are being read to perform the interpolation process.
    Type: Application
    Filed: November 25, 2003
    Publication date: August 19, 2004
    Applicant: VIma Microsystems Corporation
    Inventors: Qinggang Zhou, Clyde H. Nagakura, Sheng-Fu Wu, Andrew K. Chan
  • Publication number: 20040160528
    Abstract: A display processor integrated circuit includes a display processor portion and an on-chip programmable logic portion. The programmable logic portion can be configured to implement custom video and/or image enhancement functions. The display processor portion performs block-based motion detection. If no motion is detected for a given block of pixels, then interline gaps in the block are filled using temporal interpolation. If motion is detected, then interline gaps are filled using spatial interpolation. To maintain accuracy without unduly increasing computational complexity, a less complex high angle spatial interpolation method is employed where a low angle tilt condition is not detected. A more computationally intensive low angle spatial interpolation method can therefore be employed in low angle tilt conditions. Integrated circuit cost is reduced by employing pipelining to write parts of segment buffers at the same time that other parts are being read to perform the interpolation process.
    Type: Application
    Filed: November 25, 2003
    Publication date: August 19, 2004
    Applicant: VIma Microsystems Corporation
    Inventors: Qinggang Zhou, Clyde H. Nagakura, Sheng-Fu Wu, Andrew K. Chan
  • Publication number: 20040041918
    Abstract: A display processor integrated circuit (for example, for a television or for a digital camera) includes a display processor portion and an on-chip programmable logic portion. The on-chip programmable logic portion can be configured or programmed to implement custom video and/or image enhancement functions. Accordingly, an individual television or camera manufacturer can have his/her own custom enhancement function incorporated into the display processor integrated circuit by having the programmable logic portion configured or programmed appropriately. In one embodiment, the programming of the programmable logic portion involves changing just one mask, thereby reducing the cost, complexity and time associated with implementing tyhe custom video/image enhancement function.
    Type: Application
    Filed: September 4, 2002
    Publication date: March 4, 2004
    Inventors: Thomas M. Chan, Harry J. Raftopoulos, Andrew K. Chan
  • Patent number: 6578104
    Abstract: A RAM device, such as the type embedded in a programmable logic device, is configurable to alter the depth of the addressable elements and the width of the number of data bits received or produced by the RAM device. The RAM device includes a number of address ports for receiving the read and/or write address signals, but the RAM device may be configured such that the depth requires fewer address signals then there are address ports. Likewise, the RAM device includes a number of input and output data ports for receiving and producing the data bits, but the width of the RAM device may be configured such that the number of data bits actually received or produced are less than the number of data ports. The depth and the width of the RAM device are configured together so that the depth is increased when the width is decreased and vice versa.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: June 10, 2003
    Assignee: Quick Logic Corporation
    Inventors: Brian D. Small, Andrew K. Chan
  • Patent number: 6552410
    Abstract: A programmable circuit, such as a field programmable gate array, and a dedicated device, such as an ASIC type device, are coupled together with an antifuse based interface on a single integrated circuit. A configurable non-volatile memory that communicates with the dedicated device is also located on the integrated circuit. The platform for the programmable circuit is one half of an existing programmable circuit, which eliminates the need to engineer the programmable circuit. The programmable circuit includes a clock network that receives clock signals from clock terminals as well as from a clock network in the dedicated device. The interface between the dedicated device and programmable circuit includes a number of conductors with buffers with testing circuitry. The testing circuitry includes a PMOS test transistor and a NMOS test transistor which permits testing of the buffers without programming the antifuses coupled to the conductors.
    Type: Grant
    Filed: August 29, 2000
    Date of Patent: April 22, 2003
    Assignee: QuickLogic Corporation
    Inventors: David D. Eaton, Ket-Chong Yap, Kevin K. Yee, E. Thomas Hart, Andrew K. Chan, Neal A. Palmer, Michael W. Dini, James Apland, Panawalge S. N. Gunaratna
  • Patent number: 6542096
    Abstract: In accordance with the invention, a serializer/deserializer core of a field programmable gate array includes a channel clock and a data channel. The data channel can serialize and deserialize data in two modes. In the first mode, an embedded clock signal is recovered from the data. In the second mode, a clock signal is provided by the channel clock. A selection signal determines in which mode each of the data channels in the serializer/deserializer core operates. An stair-step clock generator generates a series of rising edge signals used to serialize and deserialize data. The number of bits serialized and deserialized is determined by the control signals to a set of multiplexers in the stair-step clock generator which determine how many registers in the stair-step clock generator are activated.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: April 1, 2003
    Assignee: QuickLogic Corporation
    Inventors: Andrew K. Chan, James M. Apland, Senani Gunaratna, SunilKumar G. Mudunuri, Ket-Chong Yap
  • Publication number: 20030039168
    Abstract: In accordance with the invention, a serializer/deserializer core of a field programmable gate array includes a channel clock and a data channel. The data channel can serialize and deserialize data in two modes. In the first mode, an embedded clock signal is recovered from the data. In the second mode, a clock signal is provided by the channel clock. A selection signal determines in which mode each of the data channels in the serializer/deserializer core operates. An stair-step clock generator generates a series of rising edge signals used to serialize and deserialize data. The number of bits serialized and deserialized is determined by the control signals to a set of multiplexers in the stair-step clock generator which determine how many registers in the stair-step clock generator are activated.
    Type: Application
    Filed: August 24, 2001
    Publication date: February 27, 2003
    Applicant: QuickLogic Corporation
    Inventors: Andrew K. Chan, James M. Apland, Senani Gunaratna, SunilKumar G. Mudunuri, Ket-Chong Yap
  • Patent number: 6519753
    Abstract: A programmable device, such as a field programmable gate array, includes a main field that is programmable by the user and at least one embedded portion that is reserved to be programmed with a standard circuit design that is configured, for example, by the manufacturer. The embedded portion is similar to the main field, i.e., it has the same programmable structure, however, the embedded portion is not accessible to the user. In some embodiments, the embedded portion may be pre-programmed with the standard circuit design and in other embodiments the embedded portion is programmed while the user programs the main field. The programmable device may also include signature bits that are used by the programming unit to identify the programmable device as having the embedded portion and which standard circuit design to program into the embedded portion. The signature bit may be programmed after the manufacture of the programmable device or may be hard wired during the manufacture of the device.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: February 11, 2003
    Assignee: QuickLogic Corporation
    Inventors: Roger Ang, Atul Ahuja, Mukesh T. Lulla, Drazen Borkovic, Brian D. Small, Charles C. Tralka, Andrew K. Chan, Kevin K. Yee
  • Patent number: 6426649
    Abstract: A field programmable gate array includes a programmable interconnect structure and plurality of logic cells. The logic cells each include a number of combinatorial logic circuits, which have direct interconnections with the programmable interconnect structure, and a plurality of sequential logic element, such as D type flip-flops that acts as registers. The combinatorial logic circuits may be directly connected to the programmable interconnect structure as well as connected to the input terminals of the sequential logic elements. Consequently, the logic cells include both combinatorial and registered connections with the programmable interconnect structure. Moreover, one of the sequential elements may selectively receive a dedicated input from the programmable interconnect structure. The output leads of the logic cell is connected to the programmable interconnect structure through a driver that includes a protection transistor.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: July 30, 2002
    Assignee: QuickLogic Corporation
    Inventors: Robert Fu, David D. Eaton, Kevin K. Yee, Andrew K. Chan
  • Publication number: 20010045495
    Abstract: Systems and methods for are described for the detection of breaks in railroad track rails as well as other events. A plurality of fiber optic monitoring assemblies are located proximate a section of railroad tracks. The monitoring assemblies are capable of detecting and recognizing a rail break event. In an alternative embodiment, systems and methods are described for detection of flat spots on rail car wheels.
    Type: Application
    Filed: March 31, 1999
    Publication date: November 29, 2001
    Inventors: LESLIE E. OLSON, STEPHEN S. ROOP, CHIN SU, ANDREW K. CHAN
  • Patent number: 6150199
    Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.
    Type: Grant
    Filed: September 27, 1999
    Date of Patent: November 21, 2000
    Assignee: QuickLogic Corporation
    Inventors: Ralph G. Whitten, Richard L. Bechtel, Mammen Thomas, Hua-Thye Chua, Andrew K. Chan, John M. Birkner
  • Patent number: 6130554
    Abstract: A programmable integrated circuit (see FIG. 13) includes a plurality of routing resources including collinearly extending routing wire segments and a test circuit for testing the integrity of the routing wire segments. The routing resource structures include a plurality of unprogrammed antifuses disposed between routing wire segments and a plurality of transistors disposed electrically in parallel with a corresponding respective one of the antifuses. The test circuit has a common node that may be coupled to a selected one of the routing resource structures for testing. In test mode, the test circuit detects whether a current flows through the selected routing resource structure and in response provides either a digital low value or a digital high value on an output node.
    Type: Grant
    Filed: September 17, 1997
    Date of Patent: October 10, 2000
    Assignee: QuickLogic Corporation
    Inventors: Paige A. Kolze, Andrew K. Chan, James A. Apland
  • Patent number: 6101074
    Abstract: A protection circuit prevents a current spike in a logic module in a field programmable gate array during power up of the gate array. The protection circuit supplies a voltage onto an internal disable input of the logic module during power up until a voltage output by a charge pump reaches a predetermined voltage. The voltage on the internal disable input turns off transistor(s) in the logic module and prevents the current spike. When the voltage output by the charge pump reaches the predetermined voltage, the protection circuit no longer supplies the voltage to the logic module's internal disable input.
    Type: Grant
    Filed: June 10, 1998
    Date of Patent: August 8, 2000
    Assignee: QuickLogic Corporation
    Inventors: James M. Apland, Andrew K. Chan