Patents by Inventor Andrew K. Chan

Andrew K. Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5280202
    Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.
    Type: Grant
    Filed: March 2, 1993
    Date of Patent: January 18, 1994
    Assignee: QuickLogic Corporation
    Inventors: Andrew K. Chan, John M. Birkner, Hua-Thye Chua
  • Patent number: 5262958
    Abstract: A processor (10) is disclosed which uses a B-spline interpolator (14) to produce a plurality of zero-level spline coefficients c.sup.0 (n). This set of coefficients may be fed to a B-spline generator (16) to produce an approximation of the input signal, and/or may be multiplied by a set of coefficients Bn to produce a set of first-level wavelet coefficients d.sup.-1 (n). The zero-level spline coefficients are also used to create first-level spline coefficients c.sup.-1 (n). The first-level spline and wavelet coefficient c.sup.-1 (n) and d.sup.-1 (n) may be submitted to a respective B-spline generator (22) or B-wavelet generator (24) to produce a first-level spline signal components and a first-level wavelet signal component for extraction of data from the original signal. The signal may in a similar fashion be decomposed to any level of resolution desired. The signal components may then be processed, and an improved signal then reassembled from the last-level spline and the processed wavelet signals.
    Type: Grant
    Filed: April 5, 1991
    Date of Patent: November 16, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Charles K. Chui, Andrew K. Chan
  • Patent number: 5243226
    Abstract: The invention allows programming an antifuse so as to reduce the antifuse resistance and the standard deviation of the resistance without increasing the programming current. This is achieved by passing current pulses of the opposite polarity through the antifuse. In some embodiments, the magnitude of the second pulse is lower than the magnitude of the first pulse. Further, if the antifuse is formed on a semiconductor substrate with one electrode on top of the other electrode and on top of the substrate, the current during the first pulse flows from the top electrode to the bottom electrode and not vice versa. A programming circuitry is provided that allows to program antifuses in a programmable circuit. A driver circuit is connected to each "horizontal" channel and each "vertical" channel. Each driver circuit is controlled by data in the driver circuit. The driver circuits are connected into shift registers so that all the data can be entered from one, two, three or four inputs.
    Type: Grant
    Filed: July 31, 1991
    Date of Patent: September 7, 1993
    Assignee: QuickLogic Corporation
    Inventor: Andrew K. Chan
  • Patent number: 5220213
    Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.
    Type: Grant
    Filed: March 6, 1992
    Date of Patent: June 15, 1993
    Assignee: Quicklogic Corporation
    Inventors: Andrew K. Chan, Hua-Thye Chua
  • Patent number: 5122685
    Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.
    Type: Grant
    Filed: March 6, 1991
    Date of Patent: June 16, 1992
    Assignee: QuickLogic Corporation
    Inventors: Andrew K. Chan, John M. Birkner, Hua-Thye Chua
  • Patent number: 5079450
    Abstract: A self-latching logic gate is disclosed which includes a first logic gate circuit for generating an output signal representative of a function of two or more input signals. The first logic gate circuit includes a first logic gate having at least two transistors, each transistor having first, second and third terminals. The first terminals of each transistor are connected to provide an output terminal for the self-latching logic gate and the first logic gate circuit. The second terminals of the transistors provide first and second data input terminals for the logic gate circuit. The third terminals of each transistor are connected to a common termination (i.e. ground). First and second complementary mode transistors are provided.
    Type: Grant
    Filed: September 13, 1990
    Date of Patent: January 7, 1992
    Assignee: Advance Micro Devices, Inc.
    Inventors: Vincent K. Z. Win, Andrew K. Chan
  • Patent number: 5057712
    Abstract: An improved address transition detector for use in PAL circuits is disclosed. The invention provides a predetermined logical output on a transition detection signal (TDS) bus for a transition of the input address on an input pad of the PAL. The TDS bus is used to trigger a phi generator which controls sense amplifiers and latch blocks on the PAL such that the circuitry is maintained in a low power stand-by mode. The detector includes a first inverter for buffering the address input to provide a first signal, a second inverter for inverting the first signal to provide a second signal and a comparator for providing the predetermined logical level on the TDS bus for a period of time after the first signal and the second signal have changed states.
    Type: Grant
    Filed: September 29, 1989
    Date of Patent: October 15, 1991
    Assignee: Advanced Micro Device, Inc.
    Inventors: Cuong Trinh, Vincent K. Z. Win, Behzad Nouban, Andrew K. Chan
  • Patent number: 5021680
    Abstract: A single, relatively simple, circuit which provides programming supply voltages for the programming circuits of a typical PAL type programmable logic array with minimal die size requirements. The invention includes a voltage charge pump circuit for providing a first voltage on a first output bus in response to a first supply voltage and an input pulse. The first output voltage provided on the first output bus is greater than the first supply voltage. The invention further includes a first circuit for switching the first supply voltage onto a second output bus in response to a first set of programming signals. A second circuit is included for switching a second supply voltage onto a second output bus in response to a second set of programming signals.
    Type: Grant
    Filed: July 31, 1989
    Date of Patent: June 4, 1991
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vincent K. Zaw Win, Andrew K. Chan
  • Patent number: 5003203
    Abstract: An adaptive reference voltage generation circuit. The invention generates a reference voltage for a sense amplifier to provide bias voltages for cells in a PAL type programmable logic array. The circuit of the invention includes a reference cell having characteristics substantially similar to the cells of the array. A reference voltage supply circuit is included for providing a reference voltage in response to any changes in the characteristics of the reference cell. In accordance with the method of the invention, the reference cell is programmed and erased whenever the cells in the array are programmed and erased. Thus the characteristics of the reference cell change in accordance with changes in the characteristics of the cells of the array.
    Type: Grant
    Filed: June 12, 1989
    Date of Patent: March 26, 1991
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vincent K. Z. Win, Andrew K. Chan
  • Patent number: 4914322
    Abstract: Polarity option control logic is disclosed which provides an optimized design for a macrocell of a programmable logic array with a minimal parts count.The invention is designed for use with a register of the macrocell having first and second input paths, the first input path including an inverter, and first and second switches in each path respectively. The polarity option control logic of the present invention includes a first logic circuit for receiving a clock input and a polarity input signal and controlling the activation of the first switch in response thereto and a second logic circuit for receiving the clock input and an inverted polarity input signal and controlling the activation of the second switch in response thereto.
    Type: Grant
    Filed: December 16, 1988
    Date of Patent: April 3, 1990
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vincent K. Z. Win, Andrew K. Chan
  • Patent number: 4789951
    Abstract: A programmable array logic cell 60 including a sum-of-products array having a single OR gate 70 for providing a sum signal, and including an XOR gate 80 for combining the sum signal with a product signal provided by an AND gate 78 from selected array input and/or feedback signals. The product signal can be the previous state output signal Q for a JK flip flop configuration, or a forced high or low signal for other configurations for programmable output signal polarity.
    Type: Grant
    Filed: May 16, 1986
    Date of Patent: December 6, 1988
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John M. Birkner, Danesh M. Tavana, Andrew K. Chan, Sing Y. Wong
  • Patent number: 4670708
    Abstract: Circuitry is provided for testing fusible link arrays for short circuits around the fusible links. Each link is electrically isolated and compared with a pair of reference fusible links to detect the presence or absence of a short circuit.
    Type: Grant
    Filed: July 30, 1984
    Date of Patent: June 2, 1987
    Assignee: Monolithic Memories, Inc.
    Inventors: Bob Bosnyak, Albert Chan, Mark Fitzpatrick, Gary Gouldsberry, Cyrus Tsui, Andrew K. Chan
  • Patent number: 4638243
    Abstract: Circuitry is provided for testing fusible link arrays for short circuits around the fusible links. Each link is electrically isolated and compared with a reference fusible link to detect the presence or absence of a short circuit.
    Type: Grant
    Filed: June 5, 1985
    Date of Patent: January 20, 1987
    Assignee: Monolithic Memories, Inc.
    Inventor: Andrew K. Chan
  • Patent number: 4625311
    Abstract: A field programmable array logic circuit is described wherein existing sensing circuitry is employed along with circuitry to enable every fuse location to be isolated, so that both a.c. and verification testing takes place under the same conditions, i.e. voltage levels and frequency, which occurs during normal operation of the programmed circuit.
    Type: Grant
    Filed: June 18, 1984
    Date of Patent: November 25, 1986
    Assignee: Monolithic Memories, Inc.
    Inventors: Mark E. Fitzpatrick, Cyrus Y. Tsui, Andrew K. Chan, Albert L. Chan