Abstract: Aspects of the invention described herein concern the incorporation of a FOXP3 cDNA (e.g., full-length human codon-optimized cDNA) into a FOXP3 gene or a non-FOXP3 locus so as to provide constitutive or regulated FOXP3 expression in a primary human CD34+ cells or cells derived from edited CD34+ cells. In some embodiments, guide RNA sequences that are directed to FOXP3, AAVS1, or other candidate loci are used for CRISPR/Cas9-mediated gene regulation, and gene delivery cassettes for HDR based gene-modification are provided.

Abstract: An H-bridge circuit formed from two sub-circuits coupled to each other by a load network across a respective load node of each of the sub-circuits. Each sub-circuit of the two sub-circuits comprises a depletion mode upper transistor with a second electrode coupled to a first electrode of a lower transistor. The load node of the sub-circuit is disposed between the second electrode of the upper transistor and the first electrode of a lower transistor. There is a first voltage supply node coupled to a first electrode of the upper transistor and a second voltage supply node is coupled to a second electrode of the lower transistor. An upper driver transistor selectively couples a gate electrode of the upper transistor to an upper drive voltage node, the upper driver transistor having a control electrode coupled to an upper switched voltage supply circuit.

Abstract: A method and apparatus for direct conversion of digital data to high power RF signals, known as DDRF. The method and apparatus receive a digital signal, create a digital modulated signal therefrom, and amplify the modulated signal with an H-bridge Power Amplifier for transmission. DDRF uses a multi-level H-bridge amplification circuit to establish a more power efficient digital transmitter.

Abstract: An H-bridge circuit formed from two sub-circuits coupled to each other by a load network across a respective load node of each of the sub-circuits. Each sub-circuit of the two sub-circuits comprises a depletion mode upper transistor with a second electrode coupled to a first electrode of a lower transistor. The load node of the sub-circuit is disposed between the second electrode of the upper transistor and the first electrode of a lower transistor. There is a first voltage supply node coupled to a first electrode of the upper transistor and a second voltage supply node is coupled to a second electrode of the lower transistor. An upper driver transistor selectively couples a gate electrode of the upper transistor to an upper drive voltage node, the upper driver transistor having a control electrode coupled to an upper switched voltage supply circuit.

Abstract: A method and apparatus for direct conversion of digital data to high power RF signals, known as DDRF. The method and apparatus receive a digital signal, create a digital modulated signal therefrom, and amplify the modulated signal with an H-bridge Power Amplifier for transmission. DDRF uses a multi-level H-bridge amplification circuit to establish a more power efficient digital transmitter.

Abstract: A tray (201) comprises electrically conductive material and has at least one hand-graspable fixture (203). This hand-graspable fixture comprises an electrical conductor (301) disposed in a location that is likely to be operably interacted with by a human who grasps the hand-graspable fixture. A capacitively-coupled RFID tag is then disposed on the hand-graspable fixture with a first antenna plate (303) being electrically coupled to the tray and a second antenna plate (304) that electrically couples to the electrical conductor. A corresponding tray receiving compartment (400) has a front lip (401) over which the tray must pass and upon which the tray will rest when properly disposed within the tray receiving compartment. One or more capacitively-coupled RFID tag reader antennas (402) are disposed proximal to the front lip. These antennas may be positioned to facilitate reading the capacitively-coupled RFID tag when the tray is properly disposed within the tray receiving compartment.

Abstract: A method and apparatus for predistortion training in an amplifier using predistortion is provided herein. Predistortion takes place by collecting a series of envelope errors and averaging the envelope errors for various amplitude regions. LUT values are modified based on a curve-fit to the average amplitude values for each amplitude region. By utilizing a curve-fitting technique, the pitfalls of modifying individual LUT coefficients is avoided. Particularly, because the errors are collected in relatively broad regions and then averaged, the importance of exact correlation between a measured error and a specific LUT entry is significantly lessened.

Abstract: An adaptive predistortion linearization system includes input path digital-to-analog converters (DACs), error path DACs, a digital signal processor, and a radio frequency (RF) combiner. The digital signal processor includes a look-up table storing complex gain coefficient values. The digital signal processor generates an error signal based on the complex input signal and the complex gain coefficients by using a vector decomposition calculation. Feedback from a power amplifier can be provided to a training algorithm for periodically updating the gain coefficient values stored in the look-up table. By performing separate D/A conversions, the error path and input signals can be separately filtered. This separation also permits the error signal to be decoupled from the complex input signal, which facilitates an improvement in the wide-frequency-offset noise performance of the system.

Abstract: An adaptive predistortion linearization system includes input path digital-to-analog converters (DACs), error path DACs, a digital signal processor, and a radio frequency (RF) combiner. The digital signal processor includes a look-up table storing complex gain coefficient values. The digital signal processor generates an error signal based on the complex input signal and the complex gain coefficients by using a vector decomposition calculation. Feedback from a power amplifier can be provided to a training algorithm for periodically updating the gain coefficient values stored in the look-up table. By performing separate D/A conversions, the error path and input signals can be separately filtered. This separation also permits the error signal to be decoupled from the complex input signal, which facilitates an improvement in the wide-frequency-offset noise performance of the system.