Patents by Inventor Andrew N Sawle
Andrew N Sawle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20180366380Abstract: A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.Type: ApplicationFiled: August 23, 2018Publication date: December 20, 2018Inventors: Mark Pavier, Andrew N. Sawle, Martin Standing
-
Patent number: 10103076Abstract: A method includes coupling a first major surface of a semiconductor die to a metallic body, depositing an insulation body over said semiconductor die, and removing a portion of said insulation body to expose a plurality of electrodes of said semiconductor die on a second major surface of said semiconductor die opposite said first surface. The method further includes forming a plurality of conductive pads over the plurality of electrodes, each conductive pad of said plurality of conductive pads providing an external connection for a respective one of said plurality of electrodes, wherein each conductive pad of said plurality of conductive pads has an area larger than an area of said respective one of said plurality of electrodes to which the respective conforming conductive pad of said plurality of conductive pads is coupled and extending over said insulation body.Type: GrantFiled: February 6, 2017Date of Patent: October 16, 2018Assignee: Infineon Technologies Americas Corp.Inventors: Mark Pavier, Andrew N. Sawle, Martin Standing
-
Patent number: 9673109Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.Type: GrantFiled: February 9, 2016Date of Patent: June 6, 2017Assignee: Infineon Technologies Americas Corp.Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
-
Publication number: 20170148692Abstract: A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.Type: ApplicationFiled: February 6, 2017Publication date: May 25, 2017Inventors: Mark Pavier, Andrew N. Sawle, Martin Standing
-
Patent number: 9633951Abstract: A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.Type: GrantFiled: November 10, 2006Date of Patent: April 25, 2017Assignee: Infineon Technologies Americas Corp.Inventors: Mark Pavier, Andrew N. Sawle, Martin Standing
-
Patent number: 9601418Abstract: According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. A current carrying layer is situated on the sync drain; the control transistor and the sync transistor being stacked on one another, where the current carrying layer provides a high current connection between the sync drain and the control source.Type: GrantFiled: March 13, 2014Date of Patent: March 21, 2017Assignee: Infineon Technologies Americas Corp.Inventors: Eung San Cho, Chuan Cheah, Andrew N. Sawle
-
Patent number: 9583477Abstract: According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal.Type: GrantFiled: May 17, 2016Date of Patent: February 28, 2017Assignee: Infineon Technologies Americas Corp.Inventors: Eung San Cho, Chuan Cheah, Andrew N. Sawle
-
Patent number: 9576887Abstract: In one implementation, a semiconductor package including conductive carrier coupled power switches includes a first vertical FET in a first active die having a first source and a first gate on a source side of the first active die and a first drain on a drain side of the first active die. The semiconductor package also includes a second vertical FET in a second active die having a second source and a second gate on a source side of the second active die and a second drain on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the first source to the second drain.Type: GrantFiled: September 9, 2013Date of Patent: February 21, 2017Assignee: Infineon Technologies Americas Corp.Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
-
Patent number: 9502395Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier.Type: GrantFiled: October 6, 2015Date of Patent: November 22, 2016Assignee: Infineon Technologies Americas Corp.Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
-
Patent number: 9461022Abstract: According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the common conductive clip, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of the common conductive clip with the common conductive clip electrically and mechanically coupling the control source with the sync drain, where the common conductive clip has a conductive leg for providing electrical and mechanical connection to an output terminal leadframe.Type: GrantFiled: May 27, 2015Date of Patent: October 4, 2016Assignee: Infineon Technologies Americas Corp.Inventors: Eung San Cho, Chuan Cheah, Andrew N. Sawle
-
Publication number: 20160260697Abstract: According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal.Type: ApplicationFiled: May 17, 2016Publication date: September 8, 2016Inventors: Eung San Cho, Chuan Cheah, Andrew N. Sawle
-
Patent number: 9397212Abstract: In one implementation, a semiconductor package includes a top-drain vertical FET in a first active die, a source of the top-drain vertical FET situated on a source side of the first active die and a drain and a gate of the top-drain vertical FET situated on a drain side of the first active die. The semiconductor package also includes a bottom-drain vertical FET in a second active die, a source and a gate of the bottom-drain vertical FET situated on a source side of the second active die and a drain of the bottom-drain vertical FET situated on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the source of the top-drain vertical FET to the drain of the bottom-drain vertical FET.Type: GrantFiled: September 9, 2013Date of Patent: July 19, 2016Assignee: Infineon Technologies Americas Corp.Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
-
Publication number: 20160155674Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.Type: ApplicationFiled: February 9, 2016Publication date: June 2, 2016Inventors: EUNG SAN CHO, ANDREW N. SAWLE, MARK PAVIER, DANIEL CUTLER
-
Patent number: 9349677Abstract: According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal.Type: GrantFiled: April 19, 2013Date of Patent: May 24, 2016Assignee: Infineon Technologies Americas Corp.Inventors: Eung San Cho, Chuan Cheah, Andrew N. Sawle
-
Patent number: 9299690Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier.Type: GrantFiled: October 6, 2015Date of Patent: March 29, 2016Assignee: Infineon Technologies Americas Corp.Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
-
Patent number: 9269655Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.Type: GrantFiled: August 13, 2015Date of Patent: February 23, 2016Assignee: Infineon Technologies Americas Corp.Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
-
Publication number: 20160035699Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier.Type: ApplicationFiled: October 6, 2015Publication date: February 4, 2016Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
-
Publication number: 20160027767Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier.Type: ApplicationFiled: October 6, 2015Publication date: January 28, 2016Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
-
Publication number: 20150348888Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.Type: ApplicationFiled: August 13, 2015Publication date: December 3, 2015Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
-
Publication number: 20150348887Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.Type: ApplicationFiled: August 13, 2015Publication date: December 3, 2015Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler