Patents by Inventor Andrew Strachan

Andrew Strachan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7067879
    Abstract: The formation of vertical trench DMOS devices can be added to existing integrated BCD process flows in order to improve the efficiency of the BCD devices. The formation of this trench DMOS varies from existing approaches used with discrete trench DMOS devices, in that only two extra mask steps are added to the existing BCD process, instead of the 10 or so mask steps used in existing discrete trench DMOS processes. Further, the location of these additional heat cycles in the BCD process steps can be placed so as to have minimal impact on the other components created in the process. Utilizing an integrated trench device in a BCD process can offer at least a factor-of-two RDS(ON) area advantage over a planar counterpart.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: June 27, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Terry Dyer, Jim McGinty, Andrew Strachan, Constantin Bulucea
  • Patent number: 6798641
    Abstract: A multiple-layer diffusion junction capacitor structure includes multiple layers of inter-digitated P-type dopant and N-type dopant formed in a semiconductor substrate. An opening in a hard mask is formed taking care to control the angle of the sidewall using a dry, anisotropic etching process. P-type and N-type dopant are then implanted at positive and negative shallow angles, respectively, each with a different energy and dose. By utilizing the properly determined implant angles, implant energies and implant doses for each of the dopant types, a high capacitance and high density diode junction capacitor, with inter-digitated N-type and P-type regions in the vertical direction is provided.
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: September 28, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Philipp Lindorfer, Vladislav Vashchenko, Andrew Strachan
  • Patent number: 6646320
    Abstract: Existing polysilicon emitter technology is used to contact poly fill in a trench isolation structure. A standard single poly emitter window process is followed. An “emitter window” is masked directly over the polysilicon trench fill. Heavily doped single emitter poly is deposited and masked over the entire active region. The standard emitter drive then diffuses dopant through the emitter window into the undoped trench poly fill to provide an ohmic contact between the emitter poly and the trench poly fill. Contact to the emitter poly is made from overlying metal.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: November 11, 2003
    Assignee: National Semiconductor Corporation
    Inventor: Andrew Strachan
  • Patent number: 6548839
    Abstract: An LDMOS array includes an array of alternating source regions and drain regions formed in a semiconductor substrate to define a checkerboard pattern of source and drain regions. A source contact is formed in electrical contact with each of the source regions in the array to connect the source regions in parallel. A drain contact is formed in electrical contact with each of the drain regions in the array to connect the drain regions in parallel. A drain ring is formed around the periphery of the checkerboard pattern and in electrical contact with the drain contact, providing redistribution of the current flow within the LDMOS array and thereby allowing safer hot carrier operation at higher biases than with the conventional layout.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: April 15, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Andrew Strachan, Douglas Brisbin