Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to protecting metal gates within transistor gate structures during SAC patterning. In particular, embodiments include area selective deposition techniques to deposit films on the gate or on a gate cap that have a good selectivity to SAC etch. In embodiments the film may include a combination of zirconium and/or oxygen, or may include zirconium oxide. Other embodiments may be described and/or claimed.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to well biasing using a buried power rail (BPR) within a circuit structure. Embodiments include using a silicide material between the BPR and a well, where the silicide material provides ohmic contact between the BPR and the well. Other embodiments may be described and/or claimed.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to a transistor structure that includes a buried power rail (BPR) located within the transistor structure at a level below a height of one or more of the fins of the transistor structure. The BPR may be located proximate to a bottom substrate of the transistor structure. In embodiments, the transistor structure includes a protective layer, which can include one or more dielectric layers, above the BPR to protect the BPR during stages of transistor structure manufacture. In embodiments, portions of the protective layer may also be used to constrain epitaxial growth during stages of manufacturing of the transistor structure. Other embodiments may be described and/or claimed.

Abstract: Described herein are transistor arrangements fabricated by forming a metal gate cut as a trench that is non-selective to the gate sidewalls, in an etch process that can remove both the gate electrode materials and the surrounding dielectrics. Such an etch process may provide improvements in terms of accuracy, cost-efficiency, and device performance, compared to conventional approaches to forming metal gate cuts. In addition, such a process may be used to provide power rails, if the trench of a metal gate cut is to be at least partially filled with an electrically conductive material. Because the electrically conductive material is in the trench and may be in between the fins, as opposed to being provided over the fins, such power rails may be referred to as “recessed.” Providing recessed power rails may provide improvements in terms of reduced metal line resistance and reduced voltage droop.

Abstract: Discussed herein is device contact sizing in integrated circuit (IC) structures. In some embodiments, an IC structure may include: a first source/drain (S/D) contact in contact with a first S/D region, and a second S/D contact in contact with a second S/D region, wherein the first S/D region and the second S/D region have a same length, and the first S/D contact and the second S/D contact have different lengths.

Abstract: Disclosed herein are source/drain regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: an array of channel regions, including a first channel region and an adjacent second channel region; a first source/drain region proximate to the first channel region; a second source/drain region proximate to the second channel region; and an insulating material region at least partially between the first source/drain region and the second source/drain region.

Abstract: Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first dielectric material continuously around the first gate metal; and a second dielectric material continuously around the second gate metal, wherein the first dielectric material and the second dielectric material are present between the first gate metal and the second gate metal.

Abstract: An example IC structure includes a plurality of elongated channel structures (e.g., fins or nanoribbons) and one or more metal gate lines crossing over the fins/nanoribbons. A buried power rail (BPR) is formed between a pair of adjacent fins/nanoribbons. Once a BPR has been formed, an opening is formed above the BPR. The opening has an elongated shape that extends horizontally along the length of the BPR and extends vertically from the top of the BPR to the top of the IC structure, cutting through the metal gate lines. Portions of the opening between cut portions of metal gate lines may be filled with a dielectric material, thus forming metal gate cuts. A portion of the opening that is not between cut portions of a metal gate line is filled with an electrically conductive material and coupled to a source/drain contact of a transistor, thus forming a conductive via.

Abstract: Disclosed herein are source/drain regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: an array of channel regions, including a first channel region and an adjacent second channel region; a first source/drain region proximate to the first channel region; a second source/drain region proximate to the second channel region; and an insulating material region at least partially between the first source/drain region and the second source/drain region.

Abstract: Disclosed herein are methods for fabricating IC structures that include stacked vias providing electrical connectivity between metal lines of different layers of a metallization stack, as well as resulting IC structures. An example IC structure includes a first and a second metallization layers, including, respectively, a bottom metal line and a top metal line. The IC structure further includes a via that has a bottom via portion and a top via portion, where the top via portion is stacked over the bottom via portion (hence, the via may be referred to as a “stacked via”). The bottom via portion is coupled and self-aligned to the bottom electrically conductive line, while the top via portion is coupled and self-aligned to the top electrically conductive line. The bottom via portion is formed using selective growth, e.g., assisted by a self-assembled monolayer (SAM) material.

Abstract: Disclosed herein are methods for fabricating IC structures that include stacked vias providing electrical connectivity between metal lines of different layers of a metallization stack, as well as resulting IC structures. An example IC structure includes a first and a second metallization layers, including, respectively, a bottom metal line and a top metal line. The IC structure further includes a via that has a bottom via portion and a top via portion, where the top via portion is stacked over the bottom via portion (hence, the via may be referred to as a “stacked via”). The bottom via portion is coupled and self-aligned to the bottom electrically conductive line, while the top via portion is coupled and self-aligned to the top electrically conductive line. The bottom via portion is formed using subtractive patterning, while the top via portion may be formed using a different fabrication technique, such as Damascene fabrication.

Abstract: Described herein are fabrication processes and resulting transistor arrangements with trench contacts that have two parts—a first trench contact (TCN1) and a second trench contact (TCN2)—stacked over one another, and with gate contacts (VCGs). In such transistor arrangements, the TCN1 may be self-aligned to adjacent gates and may be used to make cell-level connections, the TCN2 may also make cell-level connections and may be provided after the self-aligned TCN1 formation and may have an inverse taper shape, the spacer around the TCN2 may be a higher dielectric constant dielectric material than conventional spacer materials, and the VCGs may be formed without the presence of any gate caps or after using only thin temporary gate caps. Fabrication processes and transistor arrangement described herein may provide several improvements in terms of increased edge placement error margin, cost-efficiency, and device performance.

Abstract: Discussed herein is device contact sizing in integrated circuit (IC) structures. In some embodiments, an IC structure may include: a first source/drain (S/D) contact in contact with a first S/D region, and a second S/D contact in contact with a second S/D region, wherein the first S/D region and the second S/D region have a same length, and the first S/D contact and the second S/D contact have different lengths.

Abstract: Disclosed herein are isolation regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC component may include: a first region including silicon; a second region including alternating layers of a second material and a third material, wherein the second material includes silicon and germanium, the third material includes silicon, and individual ones of the layers in the second region has a thickness that is less than 3 nanometers; and a third region including alternating layers of the second material and the third material, wherein individual ones of the layers in the third region has a thickness that is greater than 3 nanometers, and the second region is between the first region and the third region.

Abstract: Gate-all-around integrated circuit structures having germanium-diffused nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium-diffused nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a sub-fin structure, wherein individual ones of the vertical arrangement of nanowires include silicon and germanium, and wherein the sub-fin structure has a relatively higher germanium concentration at a top of the sub-fin structure than at a bottom of the sub-fin structure.

Abstract: Disclosed herein are transistor arrangements with trench contacts that have two parts—a first trench contact and a second trench contact—stacked over one another. Such transistor arrangements may be fabricated by forming a first trench contact over a source or drain contact of a transistor, recessing the first trench contact, forming the second trench contact over the first trench contact, and, finally, forming a gate contact that is electrically isolated from, while being self-aligned to, the second trench contact. Such a fabrication process may provide improvements in terms of increased edge placement error margin, cost-efficiency, and device performance, compared to conventional approaches to forming trench and gate contacts. The conductive material of the first trench contact may also be deposited over the gate electrodes of transistors, forming a gate strap, to advantageously reduce gate resistance.

Abstract: Contact over active gate (COAG) structures with a tapered gate or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, wherein individual ones of the plurality gate of structures have thereon a conductive cap between sidewall spacers. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, wherein individual ones of the plurality of conductive trench contact structures have thereon a conductive cap between sidewall spacers. A conductive structure is in direct contact with the conductive cap and sidewall spacers on one of the plurality of gate structures or with the conductive cap and sidewall spacers on one of the plurality of conductive trench contact structures.

Abstract: Disclosed herein are isolation regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC component may include: a first region including silicon; a second region including alternating layers of a second material and a third material, wherein the second material includes silicon and germanium, the third material includes silicon, and individual ones of the layers in the second region has a thickness that is less than 3 nanometers; and a third region including alternating layers of the second material and the third material, wherein individual ones of the layers in the third region has a thickness that is greater than 3 nanometers, and the second region is between the first region and the third region.

Abstract: Transistor arrangements fabricated by forming a metal gate cut as an opening that is non-selective to the gate sidewalls are disclosed. The etch process may be used to provide a power rail if the opening is at least partially filled with an electrically conductive material. Once an electrically conductive material has been deposited within the opening to form a power rail, recessing such a material in portions of the power rail that face gate stacks of various transistors may provide further improvements in terms of reduced parasitic capacitance. A mask for a trench contact to be used to electrically couple the power rail to a S/D region of a transistor may be used as a mask when the electrically conductive material of the power rail is recessed to realize a via that is self-aligned to the trench contact.

Abstract: Methods for fabricating a transistor arrangement of an IC structure by using a placeholder for backside contact formation, as well as related semiconductor devices, are disclosed. An example method includes forming, in a support structure (e.g., a substrate, a chip, or a wafer), a dielectric placeholder for a backside contact as the first step in the method. A nanosheet superlattice is then grown laterally over the dielectric placeholder, and a stack of nanoribbons is formed based on the superlattice. The nanoribbons are processed to form S/D regions and gate stacks for future transistors. The dielectric placeholder remains in place until the support structure is transferred to a carrier wafer, at which point the dielectric placeholder is replaced with the backside contact. Use of a placeholder for backside contact formation allows alignment of contact from the backside to appropriate device ports of a transistor arrangement.