Patents by Inventor Andy Chih-Hung Wei

Andy Chih-Hung Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9236437
    Abstract: Embodiments of the present invention provide improved methods of contact formation. A self aligned contact scheme with reduced lithography requirements is disclosed. This reduces the risk of shorts between source/drains and gates, while providing improved circuit density. Cavities are formed adjacent to the gates, and a fill metal is deposited in the cavities to form contact strips. A patterning mask is then used to form smaller contacts by performing a partial metal recess of the contact strips.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: January 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mark A. Zaleski, Andy Chih-Hung Wei, Jason E. Stephens, Tuhin Guha Neogi, Guillaume Bouche
  • Publication number: 20160005868
    Abstract: Embodiments of the present invention provide a fin-type field effect transistor (finFET) with confined epitaxy. A protective layer is formed on a fin. The protective layer is recessed to expose the fin top. A fin cavity is formed in the fin. An epitaxial region is formed in the fin cavity. The epitaxial region has a confined portion and a diamond-shaped portion, resulting in increased epitaxial volume. The increased epitaxial volume can result in enhanced carrier mobility and improved device performance.
    Type: Application
    Filed: July 1, 2014
    Publication date: January 7, 2016
    Inventors: Andy Chih-Hung Wei, Jing Wan, Dae-Han Choi
  • Publication number: 20150380250
    Abstract: Embodiments of the present invention provide an improved structure and method of contact formation. A cap nitride is removed from a gate in a region that is distanced from a fin. This facilitates reduced process steps, allowing the gate and the source/drain regions to be opened in the same process step. Extreme Ultraviolet Lithography (EUVL) may be used to pattern the resist to form the contacts.
    Type: Application
    Filed: June 30, 2014
    Publication date: December 31, 2015
    Inventors: Andy Chih-Hung Wei, Guillaume Bouche, Gabriel Padron Wells, Xiang Hu
  • Patent number: 9224842
    Abstract: Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: December 29, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Andy Chih-Hung Wei, Xiang Hu, Jerome F. Wandell, Sandeep Gaan
  • Patent number: 9202751
    Abstract: Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: December 1, 2015
    Assignee: GlobalFoundries Inc.
    Inventors: Andy Chih-Hung Wei, Guillaume Bouche, Mark A. Zaleski, Tuhin Guha Neogi, Jason E. Stephens, Jongwook Kye, Jia Zeng
  • Publication number: 20150340467
    Abstract: Provided are approaches for forming merged gate and source/drain (S/D) contacts in a semiconductor device. Specifically, one approach provides a dielectric layer over a set of gate structures formed over a substrate; a set of source/drain (S/D) openings patterned in the dielectric layer between the gate structures; a fill material formed over the gate structures, including within the S/D openings; and a set of gate openings patterned over the gate structures, wherein a portion of the dielectric layer directly adjacent the fill material formed within one of the S/D openings is removed. The fill material is then removed, selective to the dielectric layer, and a metal material is deposited over the semiconductor device to form a set of gate contacts within the gate openings, and a set of S/D contacts within the S/D openings, wherein one of the gate contacts and one of the S/D contacts are merged.
    Type: Application
    Filed: May 20, 2014
    Publication date: November 26, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Guillaume Bouche, Andy Chih-Hung Wei
  • Publication number: 20150340461
    Abstract: Embodiments of the present invention provide a metal gate structure and method of formation. In the replacement metal gate (RMG) process flow, the gate cut process is performed after the metal gate is formed. This allows for a reduced margin between the end of the gate and an adjacent fin. It enables a thinner sacrificial layer on top of the dummy gate, since the gate cut step is deferred. The thinner sacrificial layer improves device quality by reducing the adverse effect of shadowing during implantation. Furthermore, in this process flow, the work function metal layer is terminated along the semiconductor substrate by a capping layer, which reduces undesirable shifts in threshold voltage that occurred in prior methods and structures.
    Type: Application
    Filed: May 20, 2014
    Publication date: November 26, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Andy Chih-Hung Wei, Dae G. Yang, Mariappan Hariharaputhiran, Jing Wan
  • Patent number: 9196499
    Abstract: Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: November 24, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Andy Chih-Hung Wei, Dae-han Choi, Dae Geun Yang, Xiang Hu, Mariappan Hariharaputhiran
  • Publication number: 20150311082
    Abstract: Provided are approaches for forming gate and source/drain (S/D) contacts. Specifically, a gate contact opening is formed over at least one of a set of gate structures, a set of S/D contact openings is formed over fins of the semiconductor device, and a metal material is deposited over the semiconductor device to form a gate contact within the gate contact opening and a set of S/D contacts within the set of S/D contact openings. In one approach, nitride remains between the gate contact and at least one of the S/D contacts. In another approach, the device includes merged gate and S/D contacts. This approach provides selective etching to partition areas where oxide will be further removed selectively to nitride to create cavities to metallize and create contact to the S/D, while isolation areas between contact areas are enclosed in nitride and do not get removed during the oxide etch.
    Type: Application
    Filed: April 25, 2014
    Publication date: October 29, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Guillaume Bouche, Andy Chih-Hung Wei, Gabriel Padron Wells, Andre P. Labonte, Jing Wan
  • Publication number: 20150311199
    Abstract: Embodiments of the present invention provide a multiple fin field effect transistor (finFET) with low-resistance gate structure. A metallization line is formed in parallel with the gate, and multiple contacts are formed over the fins which connect the metallization line to the gate. The metallization line provides reduced gate resistance, which allows fewer transistors to be used for providing In-Out (IO) functionality, thereby providing space savings that enable an increase in circuit density.
    Type: Application
    Filed: April 29, 2014
    Publication date: October 29, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Guillaume Bouche, Andy Chih-Hung Wei
  • Publication number: 20150303273
    Abstract: Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.
    Type: Application
    Filed: April 22, 2014
    Publication date: October 22, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Guillaume Bouche, Andy Chih-Hung Wei, Xiang Hu, Jerome F. Wandell, Sandeep Gaan
  • Publication number: 20150303295
    Abstract: Approaches for forming a set of contact openings in a semiconductor device (e.g., a FinFET device) are provided. Specifically, the semiconductor device includes a set of fins formed in a substrate, a gate structure (e.g., replacement metal gate (RMG)) formed over the substrate, and a set of contact openings adjacent the gate structure, each of the set of contact openings having a top section and a bottom section, wherein a width of the bottom section, along a length of the gate structure, is greater than a width of the top section. The semiconductor device further includes a set of metal contacts formed within the set of contact openings.
    Type: Application
    Filed: April 22, 2014
    Publication date: October 22, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Jing Wan, Xiang Hu, Jinping Liu, Gabriel Padron Wells, Andy Chih-Hung Wei, Guillaume Bouche, Cuiqin Xu
  • Patent number: 9159630
    Abstract: Approaches for providing a single spacer, double hardmask dual-epi FinFET are disclosed. Specifically, at least one approach for providing the FinFET includes: forming a set of spacers along each sidewall of a plurality of fins of the FinFET device; forming a first ultra-thin hardmask over the plurality of fins; implanting the first ultra-thin hardmask over a first set of fins from the plurality of fins; removing the first ultra-thin hardmask over a second set of fins from the plurality of fins untreated by the implant; forming an epitaxial (epi) layer over the second set of fins; forming a second ultra-thin hardmask over the FinFET device; implanting the second ultra-thin hardmask; removing the second ultra-thin hardmask over the first set of fins; and growing an epi layer over the first set of fins.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: October 13, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Andy Chih-Hung Wei, Dae Geun Yang, Dae-han Choi
  • Publication number: 20150287636
    Abstract: Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.
    Type: Application
    Filed: April 7, 2014
    Publication date: October 8, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Andy Chih-Hung Wei, Guillaume Bouche, Mark A. Zaleski, Tuhin Guha Neogi, Jason E. Stephens, Jongwook Kye, Jia Zeng
  • Publication number: 20150279684
    Abstract: Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed.
    Type: Application
    Filed: March 26, 2014
    Publication date: October 1, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Andy Chih-Hung Wei, Dae-han Choi, Dae Geun Yang, Xiang Hu, Mariappan Hariharaputhiran
  • Publication number: 20150270175
    Abstract: Provided herein are approaches for forming a fin field-effect-transistor (FinFET) device using a partially crystallized fin hard mask. Specifically, a hard mask is patterned over a substrate, and the FinFET device is annealed to form a set of crystallized hard mask elements adjacent a set of non-crystallized hard mask elements. A masking structure is provided over a first section of the patterned hard mask to prevent the set of non-crystallized hard mask elements from being crystallized during the anneal. During a subsequent fin cut process, the non-crystallized mask elements are removed, while crystallized mask elements remain. A set of fins is then formed in the FinFET device according to the location(s) of the crystallized mask elements.
    Type: Application
    Filed: March 19, 2014
    Publication date: September 24, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Xiang Hu, Andy Chih-Hung Wei, Dae-han Choi, Mariappan Hariharaputhiran, Weihua Tong, Dae Geun Yang, Akshey Sehgal, Jing Wan
  • Publication number: 20150270400
    Abstract: Approaches for altering the threshold voltage (e.g., to zero threshold voltage) in a fin-type field effect transistor (FinFET) device are provided. In embodiments of the invention, a first N+ region and a second N+ region are formed on a finned substrate that has a p-well construction. A region of the finned substrate located between the first N+ region and the second N+ region is doped with a negative implant species to form an n-well. The size and/or composition of this n-well region can be adjusted in view of the existing p-well construction of the substrate device to change the threshold voltage of the FinFET device (e.g., to yield a zero threshold voltage FinFET device).
    Type: Application
    Filed: March 18, 2014
    Publication date: September 24, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Jagar Singh, Konstantin G. Korablev, Andy Chih-Hung Wei
  • Publication number: 20150236106
    Abstract: Embodiments of the present invention provide improved methods of contact formation. A self aligned contact scheme with reduced lithography requirements is disclosed. This reduces the risk of shorts between source/drains and gates, while providing improved circuit density. Cavities are formed adjacent to the gates, and a fill metal is deposited in the cavities to form contact strips. A patterning mask is then used to form smaller contacts by performing a partial metal recess of the contact strips.
    Type: Application
    Filed: February 20, 2014
    Publication date: August 20, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Mark A. Zaleski, Andy Chih-Hung Wei, Jason E. Stephens, Tuhin Guha Neogi, Guillaume Bouche
  • Publication number: 20150214345
    Abstract: Approaches for isolating source and drain regions in an integrated circuit (IC) device (e.g., a metal-oxide-semiconductor field-effect transistor (MOSFET)) are provided. Specifically, the device comprises a gate structure formed over a substrate, a source and drain (S/D) embedded within the substrate adjacent the gate structure, and a liner layer (e.g., silicon-carbon) between the S/D and the substrate. In one approach, the liner layer is formed atop the S/D as well. As such, the liner layer formed in the junction prevents dopant diffusion from the source/drain.
    Type: Application
    Filed: January 27, 2014
    Publication date: July 30, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Jing Wan, Jinping Liu, Churamani Gaire, Mariappan Hariharaputhiran, Andy Chih-Hung Wei, Bharat V. Krishnan, Cuiqin Xu, Michael Ganz