Patents by Inventor Angela Hui
Angela Hui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10020316Abstract: A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. The inter-gate dielectric structure may be disposed between the first gate conductor and the second gate conductor, and may include two or more dielectric films disposed in an alternating manner. The second gate conductor is formed in an L shape such that the second gate has a relatively low aspect ratio, which allows for a reduction in spacing between adjacent gates, while maintaining the required electrical isolation between the gates and contacts that may subsequently be formed.Type: GrantFiled: February 15, 2017Date of Patent: July 10, 2018Assignee: Cypress Semiconductor CorporationInventors: Scott Bell, Chun Chen, Lei Xue, Shenqing Fang, Angela Hui
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Publication number: 20170162586Abstract: A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. The inter-gate dielectric structure may be disposed between the first gate conductor and the second gate conductor, and may include two or more dielectric films disposed in an alternating manner. The second gate conductor is formed in an L shape such that the second gate has a relatively low aspect ratio, which allows for a reduction it spacing between adjacent gates, while maintaining the required electrical isolation between the gates and contacts that may subsequently be formed.Type: ApplicationFiled: February 15, 2017Publication date: June 8, 2017Applicant: Cypress Semiconductor CorporationInventors: Scott Bell, Chun Chen, Lei Xue, Shenqing Fang, Angela Hui
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Patent number: 9455352Abstract: Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.Type: GrantFiled: December 17, 2013Date of Patent: September 27, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Ning Cheng, Huaqiang Wu, Hiro Kinoshita, Jihwan Choi, Angela Hui
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Publication number: 20160035576Abstract: A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. The inter-gate dielectric structure may be disposed between the first gate conductor and the second gate conductor, and may include two or more dielectric films disposed in an alternating manner. The second gate conductor is formed in an L shape such that the second gate has a relatively low aspect ratio, which allows for a reduction in spacing between adjacent gates, while maintaining the required electrical isolation between the gates and contacts that may subsequently be formed.Type: ApplicationFiled: August 4, 2014Publication date: February 4, 2016Inventors: Scott BELL, Chun CHEN, Lei XUE, Shenqing FANG, Angela HUI
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Patent number: 9245895Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.Type: GrantFiled: July 26, 2011Date of Patent: January 26, 2016Assignee: Cypress Semiconductor CorporationInventors: Ning Cheng, Kuo-Tung Chang, Hiro Kinoshita, Chih-Yuh Yang, Lei Xue, Chungho Lee, Minghao Shen, Angela Hui, Huaqiang Wu
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Publication number: 20140167138Abstract: Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.Type: ApplicationFiled: December 17, 2013Publication date: June 19, 2014Applicant: SPANSION LLCInventors: Ning Cheng, Huaqiang Wu, Hiro Kinoshita, Jihwan Choi, Angela Hui
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Patent number: 8658496Abstract: A memory device and a method of making the memory device are provided. A first dielectric layer is formed on a substrate, a floating gate is formed on the first dielectric layer, a second dielectric layer is formed on the floating gate, a control gate is formed on the second dielectric layer, and at least one film, including a conformal film, is formed over a surface of the memory device.Type: GrantFiled: September 14, 2012Date of Patent: February 25, 2014Assignees: Advanced Mirco Devices, Inc., Spansion LLCInventors: Hiroyuki Kinoshita, Angela Hui, Hsiao-Han Thio, Kuo-Tung Chang, Minh Van Ngo, Hiroyuki Ogawa
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Patent number: 8653581Abstract: Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.Type: GrantFiled: December 22, 2008Date of Patent: February 18, 2014Assignee: Spansion LLCInventors: Ning Cheng, Huaqiang Wu, Hiro Kinoshita, Jihwan Choi, Angela Hui
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Publication number: 20140001537Abstract: A method for fabricating a memory device with U-shaped trap layers over rounded active region corners is disclosed. In the present invention, an STI process is performed before the charge-trapping layer is formed. Immediately after the STI process, the sharp corners of the active regions are exposed, making them available for rounding. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, a bottom oxide layer, nitride layer, and sacrificial top oxide layer are formed. An organic bottom antireflective coating applied to the charge trapping layer is planarized. Now the organic bottom antireflective coating, sacrificial top oxide layer, and nitride layer are etched, without etching the sacrificial top oxide layer and nitride layer over the active regions. After the etching the charge trapping layer has a cross-sectional U-shape appearance.Type: ApplicationFiled: September 5, 2013Publication date: January 2, 2014Applicant: Spansion LLCInventors: Shenqing FANG, Angela HUI, Shao-Yu TING, Inkuk KANG, Gang XUE
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Patent number: 8551858Abstract: A method for fabricating a memory device with U-shaped trap layers over rounded active region corners is disclosed. In the present invention, an STI process is performed before the charge-trapping layer is formed. Immediately after the STI process, the sharp corners of the active regions are exposed, making them available for rounding. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, a bottom oxide layer, nitride layer, and sacrificial top oxide layer are formed. An organic bottom antireflective coating applied to the charge trapping layer is planarized. Now the organic bottom antireflective coating, sacrificial top oxide layer, and nitride layer are etched, without etching the sacrificial top oxide layer and nitride layer over the active regions. After the etching the charge trapping layer has a cross-sectional U-shape appearance.Type: GrantFiled: February 3, 2010Date of Patent: October 8, 2013Assignee: Spansion LLCInventors: Shenqing Fang, Angela Hui, Shao-Yu Ting, Inkuk Kang, Gang Xue
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Patent number: 8445372Abstract: Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.Type: GrantFiled: December 22, 2009Date of Patent: May 21, 2013Assignee: Spansion LLCInventors: Kyunghoon Min, Angela Hui, Hiroyuki Kinoshita, Ning Cheng, Mark Chang
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Publication number: 20130078795Abstract: A memory device and a method of making the memory device are provided. A first dielectric layer is formed on a substrate, a floating gate is formed on the first dielectric layer, a second dielectric layer is formed on the floating gate, a control gate is formed on the second dielectric layer, and at least one film, including a conformal film, is formed over a surface of the memory device.Type: ApplicationFiled: September 14, 2012Publication date: March 28, 2013Applicants: SPANSION LLC, ADVANCED MICRO DEVICES, INC.Inventors: Hiroyuki KINOSHITA, Angela HUI, Hsiao-Han THIO, Kuo-Tung CHANG, Minh VAN NGO, Hiroyuki OGAWA
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Patent number: 8384146Abstract: Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.Type: GrantFiled: March 23, 2012Date of Patent: February 26, 2013Assignee: Spansion LLCInventors: Shenqing Fang, Angela Hui, Gang Xue, Alexander Nickel, Kashmir Sahota, Scott Bell, Chun Chen, Wai Lo
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Patent number: 8319266Abstract: A memory device and a method of making the memory device are provided. A first dielectric layer is formed on a substrate, a floating gate is formed on the first dielectric layer, a second dielectric layer is formed on the floating gate, a control gate is formed on the second dielectric layer, and at least one film, including a conformal film, is formed over a surface of the memory device.Type: GrantFiled: December 10, 2004Date of Patent: November 27, 2012Assignees: Advanced Micro Devices, Inc., Spansion L.L.C.Inventors: Hiroyuki Kinoshita, Angela Hui, Hsiao-Han Thio, Kuo-Tung Chang, Minh Van Ngo, Hiroyuki Ogawa
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Publication number: 20120181601Abstract: Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.Type: ApplicationFiled: March 23, 2012Publication date: July 19, 2012Inventors: Shenqing FANG, Angela HUI, Gang XUE, Alexander NICKEL, Kashmir SAHOTA, Scott BELL, Chun CHEN, Wai LO
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Patent number: 8202779Abstract: Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.Type: GrantFiled: September 27, 2010Date of Patent: June 19, 2012Assignee: Spansion LLCInventors: Shenqing Fang, Angela Hui, Gang Xue, Alexander Nickel, Kashmir Sahota, Scott Bell, Chun Chen, Wai Lo
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Patent number: 8093646Abstract: The present invention provides a flash memory device and method for making the same having a floating gate structure with a semiconductor substrate and shallow trench isolation (STI) structure formed in the substrate. A first polysilicon layer is formed over the substrate and the STI structure. The recess formed within the first polysilicon layer is over the STI structure and extends through the first polysilicon layer to the STI structure. An oxide fill is provided within the recess and is etched back. ONO (oxide-nitride-oxide) layer conformally covers the oxide fill and the first polysilicon layer. The second polysilicon layer covers the ONO layer. The oxide fill within the recess provides a minimum spacing between the second polysilicon layer and the corner of the STI regions, thereby avoiding the creation of a weak spot and reducing the risk of gate breakdown, gate leakage, and improving device reliability.Type: GrantFiled: May 12, 2006Date of Patent: January 10, 2012Assignee: Spansion LLCInventors: Angela Hui, Yider Wu
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Publication number: 20110278660Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.Type: ApplicationFiled: July 26, 2011Publication date: November 17, 2011Applicant: SPANSION LLCInventors: Ning Cheng, K.T. Chang, Hiro Kinoshita, Chih-Yuh Yang, Lei Xue, Chungho Lee, Minghao Shen, Angela Hui, Huaqiang Wu
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Patent number: 8035153Abstract: A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.Type: GrantFiled: May 26, 2010Date of Patent: October 11, 2011Assignee: Spansion LLCInventors: Shenqing Fang, Jihwan Choi, Calvin Gabriel, Fei Wang, Angela Hui, Alexander Nickel, Zubin Patel, Phillip Jones, Mark Chang, Minh-Van Ngo
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Publication number: 20110233647Abstract: Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.Type: ApplicationFiled: September 27, 2010Publication date: September 29, 2011Inventors: Shenqing FANG, Angela HUI, Gang XUE, Alexander NICKEL, Kashmir SAHOTA, Scott BELL, Chun CHEN, Wai LO