Patents by Inventor Angela Kessler

Angela Kessler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210035879
    Abstract: A package and method of manufacturing a package is disclosed. In one example, the method comprises mounting at least one electronic component on a carrier, attaching a laminate body to the mounted at least one electronic component, and filling at least part of spaces between the laminate body and the carrier with mounted at least one electronic component with an encapsulant.
    Type: Application
    Filed: July 30, 2020
    Publication date: February 4, 2021
    Applicant: Infineon Technologies AG
    Inventors: Angela Kessler, Thorsten Scharf
  • Publication number: 20210035876
    Abstract: A semiconductor package is disclosed. In one example, the semiconductor package includes a package body and a semiconductor component encapsulated in the package body. A cavity is formed in a bottom surface of the package body.
    Type: Application
    Filed: July 27, 2020
    Publication date: February 4, 2021
    Applicant: Infineon Technologies AG
    Inventors: Ralf Otremba, Markus Dinkel, Josef Hoeglauer, Angela Kessler
  • Publication number: 20200402881
    Abstract: A die package is provided. The die package may include a laminated carrier including at least one recess, a first die having a frontside, a backside, a frontside metallization on the frontside and a backside metallization on the backside, wherein the first die is arranged in the at least one recess, a first encapsulating material partially encapsulating the first die, by covering at least the frontside metallization or the backside metallization, and an adhesion promoter material between the metallization covered by the first encapsulation material and the first encapsulation material and in direct physical contact with the first encapsulation material and the metallization covered by the first encapsulation material.
    Type: Application
    Filed: June 23, 2020
    Publication date: December 24, 2020
    Inventors: Petteri Palm, Angela Kessler
  • Publication number: 20200176412
    Abstract: A package and method of making a package is disclosed. In one example, the package includes an electronic chip having at least one pad, an encapsulant at least partially encapsulating the electronic chip, and an electrically conductive contact element extending from the at least one pad and through the encapsulant so as to be exposed with respect to the encapsulant. The electrically conductive contact element comprises a first contact structure made of a first electrically conductive material on the at least one pad and comprises a second contact structure made of a second electrically conductive material and being exposed with respect to the encapsulant. At least one of the at least one pad has at least a surface portion which comprises or is made of the first electrically conductive material.
    Type: Application
    Filed: November 21, 2019
    Publication date: June 4, 2020
    Applicant: Infineon Technologies AG
    Inventors: Angela Kessler, Andreas Grassmann
  • Patent number: 10615097
    Abstract: A chip carrier which comprises a thermally conductive and electrically insulating sheet, a first electrically conductive structure on a first main surface of the sheet, and a second electrically conductive structure on a second main surface of the sheet, wherein the first electrically conductive structure and the second electrically conductive structure extend beyond a lateral edge of the sheet.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: April 7, 2020
    Assignee: Infineon Technologies AG
    Inventors: Andreas Grassmann, Wolfram Hable, Juergen Hoegerl, Angela Kessler, Ivan Nikitin, Achim Strass
  • Patent number: 10586756
    Abstract: A chip carrier for carrying an electronic chip, wherein the chip carrier comprises a mounting section configured for mounting an electronic chip by sintering, and an encapsulation section configured for being encapsulated by an encapsulant.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: March 10, 2020
    Assignee: Infineon Technologies AG
    Inventors: Alexander Roth, Andreas Grassmann, Juergen Hoegerl, Angela Kessler
  • Publication number: 20190157192
    Abstract: A package comprising at least one electronic chip, a first heat removal body on which the at least one electronic chip is mounted by a first interconnection, a second heat removal body mounted on or above the at least one electronic chip by a second interconnection, and an encapsulant encapsulating at least part of the at least one electronic chip, part of the first heat removal body and part of the second heat removal body, wherein the first interconnection is configured to have another melting temperature than the second interconnection.
    Type: Application
    Filed: January 3, 2019
    Publication date: May 23, 2019
    Inventors: Andreas Grassmann, Juergen Hoegerl, Angela Kessler, Ivan Nikitin
  • Patent number: 10283432
    Abstract: A method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces; a mounting at least one electronic chip on the chip carrier; an electrically coupling an electrically conductive contact structure with the at least one electronic chip; and an encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: May 7, 2019
    Assignee: Infineon Technologies AG
    Inventors: Mark Pavier, Wolfram Hable, Angela Kessler, Michael Sielaff, Anton Pugatschow, Charles Rimbert-Riviere, Marco Sobkowiak
  • Patent number: 10242969
    Abstract: A semiconductor package includes a first semiconductor module including a plurality of semiconductor transistor chips and a first encapsulation layer disposed above the semiconductor transistor chips, and a second semiconductor module disposed above the first semiconductor module. The second semiconductor module includes a plurality of semiconductor driver channels and a second encapsulation layer disposed above the semiconductor driver channels. The semiconductor driver channels are configured to drive the semiconductor transistor chips.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: March 26, 2019
    Assignee: Infineon Technologies AG
    Inventors: Olaf Hohlfeld, Juergen Hoegerl, Angela Kessler, Magdalena Hoier
  • Patent number: 10211133
    Abstract: A package comprising at least one electronic chip, a first heat removal body on which the at least one electronic chip is mounted by a first interconnection, a second heat removal body mounted on or above the at least one electronic chip by a second interconnection, and an encapsulant encapsulating at least part of the at least one electronic chip, part of the first heat removal body and part of the second heat removal body, wherein the first interconnection is configured to have another melting temperature than the second interconnection.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: February 19, 2019
    Assignee: Infineon Technologies AG
    Inventors: Andreas Grassmann, Juergen Hoegerl, Angela Kessler, Ivan Nikitin
  • Publication number: 20190006260
    Abstract: A method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces; a mounting at least one electronic chip on the chip carrier; an electrically coupling an electrically conductive contact structure with the at least one electronic chip; and an encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant.
    Type: Application
    Filed: August 24, 2018
    Publication date: January 3, 2019
    Inventors: Mark PAVIER, Wolfram HABLE, Angela KESSLER, Michael SIELAFF, Anton PUGATSCHOW, Charles RIMBERT-RIVIERE, Marco SOBKOWIAK
  • Patent number: 10128180
    Abstract: A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: November 13, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Michael Bauer, Alfred Haimerl, Angela Kessler, Wolfgang Schober
  • Patent number: 10074590
    Abstract: A package which comprises a chip carrier, at least one electronic chip mounted on the chip carrier, an electrically conductive contact structure electrically coupled with the at least one electronic chip, and a mold-type encapsulant encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip, wherein the chip carrier comprises a thermally conductive and electrically insulating core covered on both opposing main surfaces thereof by a respective brazed electrically conductive layer.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: September 11, 2018
    Assignee: Infineon Technologies AG
    Inventors: Mark Pavier, Wolfram Hable, Angela Kessler, Michael Sielaff, Anton Pugatschow, Charles Rimbert-Riviere, Marco Sobkowiak
  • Patent number: 10062671
    Abstract: A semiconductor module includes a circuit board and a power semiconductor chip embedded in the circuit board. The power semiconductor chip has a first load electrode. The semiconductor module further includes a power terminal connector electrically connected to the first load electrode. The embedded power semiconductor chip is positioned laterally within a footprint zone of the power terminal connector.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: August 28, 2018
    Assignee: Infineon Technologies AG
    Inventors: Martin Gruber, Angela Kessler, Thorsten Scharf
  • Publication number: 20180138111
    Abstract: A package comprising at least one electronic chip, a first heat removal body on which the at least one electronic chip is mounted by a first interconnection, a second heat removal body mounted on or above the at least one electronic chip by a second interconnection, and an encapsulant encapsulating at least part of the at least one electronic chip, part of the first heat removal body and part of the second heat removal body, wherein the first interconnection is configured to have another melting temperature than the second interconnection.
    Type: Application
    Filed: November 13, 2017
    Publication date: May 17, 2018
    Inventors: Andreas Grassmann, Juergen Hoegerl, Angela Kessler, Ivan Nikitin
  • Publication number: 20180102302
    Abstract: A chip carrier which comprises a thermally conductive and electrically insulating sheet, a first electrically conductive structure on a first main surface of the sheet, and a second electrically conductive structure on a second main surface of the sheet, wherein the first electrically conductive structure and the second electrically conductive structure extend beyond a lateral edge of the sheet.
    Type: Application
    Filed: October 12, 2017
    Publication date: April 12, 2018
    Inventors: Andreas GRASSMANN, Wolfram HABLE, Juergen HOEGERL, Angela KESSLER, Ivan NIKITIN, Achim STRASS
  • Publication number: 20180096924
    Abstract: A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material.
    Type: Application
    Filed: November 24, 2017
    Publication date: April 5, 2018
    Inventors: Michael Bauer, Alfred Haimerl, Angela Kessler, Wolfgang Schober
  • Publication number: 20180096919
    Abstract: A chip carrier for carrying an electronic chip, wherein the chip carrier comprises a mounting section configured for mounting an electronic chip by sintering, and an encapsulation section configured for being encapsulated by an encapsulant.
    Type: Application
    Filed: October 3, 2017
    Publication date: April 5, 2018
    Inventors: Alexander ROTH, Andreas GRASSMANN, Juergen HOEGERL, Angela KESSLER
  • Patent number: 9859198
    Abstract: A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: January 2, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Michael Bauer, Alfred Haimerl, Angela Kessler, Wolfgang Schober
  • Publication number: 20170278762
    Abstract: A package comprising an electronic chip, a laminate type encapsulant in and/or on which the electronic chip is mounted, a solderable electric contact on a solder surface of the package, and a solder flow path on and/or in the package which is configured so that, upon soldering the electric contact with a mounting base, part of solder material flows along the solder flow path towards a surface of the package at which the solder material is optically inspectable after completion of the solder connection between the mounting base and the electric contact.
    Type: Application
    Filed: March 23, 2017
    Publication date: September 28, 2017
    Inventors: Angela KESSLER, Oliver HAEBERLEN, Matteo-Alessandro KUTSCHAK, Ralf OTREMBA, Petteri PALM, Boris PLIKAT, Thorsten SCHARF, Klaus SCHIESS, Fabian SCHNOY, Erich SYRI