Abstract: A semiconductor device includes: a semiconductor body having an active region and an edge termination region between the active region and a side surface of the semiconductor body; a first portion including silicon and nitrogen; a second portion including silicon and nitrogen, the second portion being in direct contact with the first portion; and a front side metallization in contact with the semiconductor body in the active region. The first portion separates the second portion from the semiconductor body. An average silicon content in the first portion is higher than in the second portion. The front side metallization is interposed between the first portion and the semiconductor body in the active region but not in the edge termination region, and/or the first portion and the second portion are both present in the edge termination region but not in the active region.

Abstract: A high voltage semiconductor device includes a semiconductor substrate including an upper surface, a high voltage electrically conductive structure disposed on the semiconductor substrate, a first step topography at an edge of the high voltage electrically conductive structure, a varying lateral doping zone disposed within the semiconductor substrate, and a layer stack including an electrically insulating buffer layer, a SiC layer over the electrically insulating buffer layer, and a silicon nitride layer over the SiC layer or a nitrided surface region of the SiC layer, wherein the layer stack conforms to the first step topography and extends over the varying lateral doping zone.

Abstract: A semiconductor device and a method of forming a semiconductor device are provided. In an embodiment, the semiconductor device comprises a device region, an edge termination region surrounding the device region, a first metal feature in the edge termination region, a first conformal ion diffusion barrier layer over the first metal feature, and a first conformal chemical protection layer over the first conformal ion diffusion barrier layer.

Abstract: A power semiconductor device having a power semiconductor transistor configuration includes: a semiconductor body having a front side coupled to a first load terminal structure, a backside coupled to a second load terminal structure, and a lateral chip edge; an active region for conducting a load current in a conducting state; and an edge termination region separating the active region and lateral chip edge. At the front-side, the edge termination region includes a protection region devoid of any metallic structure, unless the metallic structure is electrically shielded from below by a polysilicon layer that extends further towards the lateral chip edge than the metallic structure by a lateral distance of at least 20 ?m. In a blocking state, the protection region accommodates a voltage change of at least 90% of a blocking voltage inside the semiconductor body in a lateral direction from the active region towards the lateral chip edge.

Abstract: A semiconductor device includes: a semiconductor body having an active region and an edge termination region between the active region and a side surface of the semiconductor body; a first portion including silicon and nitrogen; a second portion including silicon and nitrogen, the second portion being in direct contact with the first portion; and a front side metallization in contact with the semiconductor body in the active region. The first portion separates the second portion from the semiconductor body. An average silicon content in the first portion is higher than in the second portion. The front side metallization is interposed between the first portion and the semiconductor body in the active region but not in the edge termination region, and/or the first portion and the second portion are both present in the edge termination region but not in the active region.

Abstract: A semiconductor device includes a semiconductor body and a first portion including silicon and nitrogen. The first portion is in direct contact with the semiconductor body. A second portion including silicon and nitrogen is in direct contact with the first portion. The first portion is between the semiconductor body and the second portion. An average silicon content in the first portion is higher than in the second portion.

Abstract: A high voltage semiconductor device includes a high voltage electrically conductive structure and a step topography at or in the vicinity of the high voltage electrically conductive structure. A layer stack covers the step topography. The layer stack includes an electrically insulating buffer layer, a SiC layer over the electrically insulating buffer layer and a silicon nitride layer over the SiC layer or a nitrided surface region of the SiC layer.

Abstract: A power semiconductor device having a power semiconductor transistor configuration includes: a semiconductor body having a front side coupled to a first load terminal structure, a backside coupled to a second load terminal structure, and a lateral chip edge; an active region for conducting a load current in a conducting state; and an edge termination region separating the active region and lateral chip edge. At the front-side, the edge termination region includes a protection region devoid of any metallic structure, unless the metallic structure is electrically shielded from below by a polysilicon layer that extends further towards the lateral chip edge than the metallic structure by a lateral distance of at least 20 ?m. In a blocking state, the protection region accommodates a voltage change of at least 90% of a blocking voltage inside the semiconductor body in a lateral direction from the active region towards the lateral chip edge.

Abstract: A semiconductor device includes a semiconductor body and a first portion including silicon and nitrogen. The first portion is in direct contact with the semiconductor body. A second portion including silicon and nitrogen is in direct contact with the first portion. The first portion is between the semiconductor body and the second portion. An average silicon content in the first portion is higher than in the second portion.

Abstract: A method for manufacturing a high-voltage semiconductor device includes exposing a semiconductor substrate to a plasma to form a protective substance layer on the semiconductor substrate. A semiconductor device includes a semiconductor substrate and a protective substance layer on the semiconductor substrate.

Abstract: A semiconductor arrangement is presented.

Abstract: A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer.

Abstract: A semiconductor arrangement is presented.

Abstract: A semiconductor arrangement is presented.

Abstract: A semiconductor arrangement is presented.

Abstract: A semiconductor device includes a semiconductor substrate having a first side, a second side opposite the first side, an active area, an outer rim, and an edge termination area arranged between the outer rim and the active area. A metallization structure is arranged on the first side of the semiconductor substrate and comprising at least a first metal layer comprised of a first metallic material and a second metal layer comprised of a second metallic material, wherein the first metallic material is electrochemically more stable than the second metallic material. The first metal layer extends laterally further towards the outer rim than the second metal layer.

Abstract: A power semiconductor device in accordance with various embodiments may include: a semiconductor body; and a passivation layer disposed over at least a portion of the semiconductor body, wherein the passivation layer includes an organic dielectric material having a water uptake of less than or equal to 0.5 wt % in saturation.

Abstract: A semiconductor device includes a semiconductor substrate having a first side, a second side opposite the first side, an active area, an outer rim, and an edge termination area arranged between the outer rim and the active area. A metallization structure is arranged on the first side of the semiconductor substrate and comprising at least a first metal layer comprised of a first metallic material and a second metal layer comprised of a second metallic material, wherein the first metallic material is electrochemically more stable than the second metallic material. The first metal layer extends laterally further towards the outer rim than the second metal layer.

Abstract: A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer.

Abstract: A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer.