Patents by Inventor Anh T. Hoang

Anh T. Hoang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9541603
    Abstract: A method and apparatus for power glitch detection in IC's is disclosed. In one embodiment, a method includes a detection circuit in an IC detecting a voltage transient wherein a value of a supply voltage has at least momentarily fallen below a reference voltage value. Responsive thereto, the detection circuit may cause a logic value to be stored in a register indicating that the detection circuit has detected the supply voltage falling below the reference voltage. The IC may include a number of detection circuits coupled to the register, each of which may provide a corresponding indication of detecting the supply voltage falling below the reference voltage. The detection circuits may be placed at different locations, and thus reading the register may yield information indicating the locations where, if any, such voltage transients occurred.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: January 10, 2017
    Assignee: Apple Inc.
    Inventors: Brian S. Park, Patrick D. McNamara, Kwang M. Lee, Meng C. Chong, Geertjan Joordens, Raman S. Thiara, Anh T. Hoang, John P. Gonzalez
  • Publication number: 20150015283
    Abstract: A method and apparatus for power glitch detection in IC's is disclosed. In one embodiment, a method includes a detection circuit in an IC detecting a voltage transient wherein a value of a supply voltage has at least momentarily fallen below a reference voltage value. Responsive thereto, the detection circuit may cause a logic value to be stored in a register indicating that the detection circuit has detected the supply voltage falling below the reference voltage. The IC may include a number of detection circuits coupled to the register, each of which may provide a corresponding indication of detecting the supply voltage falling below the reference voltage. The detection circuits may be placed at different locations, and thus reading the register may yield information indicating the locations where, if any, such voltage transients occurred.
    Type: Application
    Filed: July 10, 2013
    Publication date: January 15, 2015
    Inventors: Brian S. Park, Patrick D. McNamara, Kwang M. Lee, Meng C. Chong, Geertjan Joordens, Raman S. Thiara, Anh T. Hoang, John P. Gonzalez
  • Patent number: 8904248
    Abstract: A self-test loopback apparatus for an interface is disclosed. In one embodiment, a bidirectional interface of an integrated circuit includes a transmitter coupled to an external pin, a first receiver coupled to the external pin, and a second receiver coupled to the external pin. During operation in a test mode, the first receiver may be disabled. The transmitter may transmit test patterns generated by a built-in self-test (BIST) circuit, and compare those test patterns to patterns received by the second receiver. The second receiver may be implemented as a Schmitt trigger (wherein the first receiver may be a standard single-bit comparator). When operating in functional mode, the second receiver may be disabled.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: December 2, 2014
    Assignee: Apple Inc.
    Inventors: Brian S. Park, Gregory S. Scott, Anh T. Hoang
  • Patent number: 8836366
    Abstract: A system and method for testing circuits. A generated input voltage waveform for a first phase of a test may use transitions with a voltage swing between expected low and high trigger points for an integrated circuit (IC) with hysteresis. A generated input voltage waveform for a second phase of the test may use transitions with a voltage swing between the expected low trigger point and a high sub-threshold value. The high sub-threshold value may be a tolerable voltage difference below the expected high trigger point. A generated input voltage waveform for a third phase of the test may use transitions with a voltage swing between the expected high trigger point and a low sub-threshold value. The low sub-threshold value may be a tolerable voltage difference above the expected low trigger point. The expected trigger points and sub-threshold values may be found from earlier characterization studies for the IC.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: September 16, 2014
    Assignee: Apple Inc.
    Inventors: Anh T. Hoang, Brian S. Park, Patrick D. McNamara
  • Patent number: 8793545
    Abstract: A method and apparatus for detecting clock glitches during at-speed testing of integrated circuits is disclosed. In one embodiment, an integrated circuit includes a scan chain having a number of scan elements coupled in a series configuration. Each of the scan elements is coupled to receive a clock signal that may be cycled during a test operation. A subset of the scan elements are arranged to form, along with other components, a counter. Test stimulus data shifted into the scan chain to perform a test may include an initial count value that is shifted into the scan elements of the counter. When the test is performed, the count value is updated responsive to cycling of the clock signal. The updated count value is shifted from the counter along with other test result data, and may be used to determine if the number of clock cycles received during the test.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: July 29, 2014
    Assignee: Apple Inc.
    Inventors: Ravi K. Ramaswami, Samy R. Makar, Anh T. Hoang
  • Publication number: 20140019817
    Abstract: A self-test loopback apparatus for an interface is disclosed. In one embodiment, a bidirectional interface of an integrated circuit includes a transmitter coupled to an external pin, a first receiver coupled to the external pin, and a second receiver coupled to the external pin. During operation in a test mode, the first receiver may be disabled. The transmitter may transmit test patterns generated by a built-in self-test (BIST) circuit, and compare those test patterns to patterns received by the second receiver. The second receiver may be implemented as a Schmitt trigger (wherein the first receiver may be a standard single-bit comparator). When operating in functional mode, the second receiver may be disabled.
    Type: Application
    Filed: July 10, 2012
    Publication date: January 16, 2014
    Inventors: Brian S. Park, Gregory S. Scott, Anh T. Hoang
  • Publication number: 20140013173
    Abstract: A method and apparatus for detecting clock glitches during at-speed testing of integrated circuits is disclosed. In one embodiment, an integrated circuit includes a scan chain having a number of scan elements coupled in a series configuration. Each of the scan elements is coupled to receive a clock signal that may be cycled during a test operation. A subset of the scan elements are arranged to form, along with other components, a counter. Test stimulus data shifted into the scan chain to perform a test may include an initial count value that is shifted into the scan elements of the counter. When the test is performed, the count value is updated responsive to cycling of the clock signal. The updated count value is shifted from the counter along with other test result data, and may be used to determine if the number of clock cycles received during the test.
    Type: Application
    Filed: July 3, 2012
    Publication date: January 9, 2014
    Inventors: Ravi K. Ramaswami, Samy R. Makar, Anh T. Hoang
  • Publication number: 20130088254
    Abstract: A system and method for testing circuits. A generated input voltage waveform for a first phase of a test may use transitions with a voltage swing between expected low and high trigger points for an integrated circuit (IC) with hysteresis. A generated input voltage waveform for a second phase of the test may use transitions with a voltage swing between the expected low trigger point and a high sub-threshold value. The high sub-threshold value may be a tolerable voltage difference below the expected high trigger point. A generated input voltage waveform for a third phase of the test may use transitions with a voltage swing between the expected high trigger point and a low sub-threshold value. The low sub-threshold value may be a tolerable voltage difference above the expected low trigger point. The expected trigger points and sub-threshold values may be found from earlier characterization studies for the IC.
    Type: Application
    Filed: April 24, 2012
    Publication date: April 11, 2013
    Inventors: Anh T. Hoang, Brian S. Park, Patrick D. McNamara