Patents by Inventor Anil Kumar Kandala
Anil Kumar Kandala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11127718Abstract: Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack that includes chips. One or more chips each includes a selection circuit and a broken via pillar that includes first and second continuous portions. The first continuous portion includes a through substrate via and a first metal line. The second continuous portion includes a second metal line. The first and second metal lines are disposed within dielectric layers disposed on a side of the semiconductor substrate of the respective chip. The first and second continuous portions are aligned in a direction normal to the side of the semiconductor substrate. An input node of the selection circuit is connected to one of the first or second metal line. An output node of the selection circuit is connected to the other of the first or second metal line.Type: GrantFiled: January 13, 2020Date of Patent: September 21, 2021Assignee: XILINX, INC.Inventors: Anil Kumar Kandala, Vijay Kumar Koganti, Santosh Yachareni
-
Publication number: 20210217729Abstract: Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack that includes chips. One or more chips each includes a selection circuit and a broken via pillar that includes first and second continuous portions. The first continuous portion includes a through substrate via and a first metal line. The second continuous portion includes a second metal line. The first and second metal lines are disposed within dielectric layers disposed on a side of the semiconductor substrate of the respective chip. The first and second continuous portions are aligned in a direction normal to the side of the semiconductor substrate. An input node of the selection circuit is connected to one of the first or second metal line. An output node of the selection circuit is connected to the other of the first or second metal line.Type: ApplicationFiled: January 13, 2020Publication date: July 15, 2021Inventors: Anil Kumar KANDALA, Vijay Kumar KOGANTI, Santosh YACHARENI
-
Patent number: 11004833Abstract: Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack that includes chips. Neighboring chips are connected to each other. Plural chips of the chips collectively include columns of broken via pillars and bridges. Each of the plural chips has a broken via pillar in each column. The broken via pillar has first and second continuous via pillar portions aligned in a direction normal to a side of a semiconductor substrate of the respective chip. The first continuous via pillar portion is not connected within the broken via pillar to the second continuous via pillar portion. Each of the plural chips has one or more of the bridges. Each bridge connects, within the respective chip, the first continuous via pillar portion in a column and the second continuous via pillar portion in another column.Type: GrantFiled: February 17, 2020Date of Patent: May 11, 2021Assignee: XILINX, INC.Inventors: Anil Kumar Kandala, Vijay Kumar Koganti, Santosh Yachareni, Sundeep Ram Gopal Agarwal
-
Patent number: 10886921Abstract: Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack including a base chip and two or more overlying chips overlying the base chip. Neighboring chips of the chip stack are connected to each other. The chip stack includes identification generation connections and circuits configured to generate a unique identification of each overlying chip based on a relative position of the respective overlying chip with reference to the base chip. The chip stack includes a communication channel from the base chip to each overlying chip. Each overlying chip includes comparison and enable/disable logic (CEDL) communicatively coupled to the communication channel. The CEDL is configured to compare a target identification of data received by the respective overlying chip to the unique identification of the respective overlying chip and responsively enable or disable a recipient circuit of the respective overlying chip.Type: GrantFiled: March 20, 2020Date of Patent: January 5, 2021Assignee: XILINX, INC.Inventors: Vijay Kumar Koganti, Anil Kumar Kandala, Santosh Yachareni
-
Patent number: 10466275Abstract: Apparatus and associated methods relate to a glitch detection circuit monitoring a duration that a selected fractional supply voltage is below a predetermined voltage threshold. The selected fractional supply voltage may be at the predetermined threshold when the supply voltage is between a valid circuit-supply voltage and a power-on circuit-reset (POR). A glitch detect signal may be generated, for example, when the monitored duration is greater than a predetermined duration threshold. A test glitch generator may generate a test glitch, for example, having selectable voltage and duration, which may be selectably applied to the glitch detection circuit to verify operation.Type: GrantFiled: June 28, 2018Date of Patent: November 5, 2019Assignee: XILINX, INC.Inventors: Sandeep Vundavalli, Sree RKC Saraswatula, James D. Wesselkamper, Santosh Yachareni, Shidong Zhou, Anil Kumar Kandala
-
Patent number: 10069487Abstract: A disclosed delay circuit includes a plurality of Schmitt triggers that are serially coupled. A first Schmitt trigger of the plurality of Schmitt triggers is configured to receive an input signal. An output control circuit is coupled to receive output signals of two or more Schmitt triggers of the plurality of Schmitt triggers, the output control circuit configured to select a signal from one of the one or more Schmitt triggers as an output signal. The output signal is a delayed version of the input signal.Type: GrantFiled: March 20, 2017Date of Patent: September 4, 2018Assignee: XILINX, INC.Inventors: Anil Kumar Kandala, Santosh Yachareni, Sandeep Vundavalli, Vijay Kumar Koganti, Golla V S R K Prasad, Udaya Kumar Bobbili
-
Patent number: 9680474Abstract: An interconnect element includes: a selection circuit for receiving input signals and having a selection output; a half-latch circuit having an input coupled to the selection output, wherein the half latch circuit comprises a pull-up device; and a common bias circuit coupled to the pull-up device, wherein the common bias circuit is configured to supply a tunable bias voltage to the pull-up device.Type: GrantFiled: March 17, 2016Date of Patent: June 13, 2017Assignee: XILINX, INC.Inventors: Anil Kumar Kandala, Srinivasa L. Karumajji, Santosh Yachareni, Sandeep Vundavalli, Udaya Kumar Bobbili, Golla V S R K Prasad
-
Patent number: 9634648Abstract: A circuit includes a divider circuit block configured to generate a trim term signal (VBG_TRIM) that is temperature and process independent. The circuit further includes a processing circuit block configured to multiply a temperature dependent reference voltage signal (TAP_GG) by a factor, and to sum the trim term signal with a result of the multiplication to generate an output reference voltage (VGG).Type: GrantFiled: December 5, 2013Date of Patent: April 25, 2017Assignee: XILINX, INC.Inventors: Shidong Zhou, Anil Kumar Kandala, Narendra Kumar Pulipati, Santosh Yachareni
-
Interconnect multiplexers and methods of reducing contention currents in an interconnect multiplexer
Patent number: 9509307Abstract: An interconnect multiplexer comprises a plurality of CMOS pass gates of a first multiplexer stage coupled to receive data to be output by the interconnect multiplexer; an output inverter coupled to the outputs of the plurality of CMOS pass gates, wherein an output of the output inverter is an output of the interconnect multiplexer; and a plurality of memory elements coupled to the plurality of CMOS pass gates; wherein inputs to the plurality of CMOS pass gates are pulled to a common potential during a startup mode. A method of reducing contention currents in an integrated circuit is also disclosed.Type: GrantFiled: September 22, 2014Date of Patent: November 29, 2016Assignee: XILINX, INC.Inventors: Vikram Santurkar, Anil Kumar Kandala, Santosh Yachareni, Shidong Zhou, Robert Fu, Philip Costello, Sandeep Vundavalli, Steven P. Young, Brian C. Gaide -
Patent number: 9166584Abstract: An apparatus is disclosed for communication of data signals in a current-encoded format. The apparatus includes a first logic block and a second logic block. The first logic block includes a first voltage-mode logic (VML) circuit configured to provide a first voltage-encoded binary signal and an encoder circuit configured to convert the voltage-encoded binary signal to a current-encoded binary signal. The second logic block includes a decoder circuit configured to receive the current-encoded binary signal from the first logic block and convert the current-encoded binary signal to a second voltage-encoded binary signal. The logic states encoded by the second voltage-encoded binary signal are equal to the logic states encoded by the first voltage-encoded binary signal. The second logic block also includes a second VML circuit coupled to the decoder circuit and configured to receive and process the second voltage-encoded binary signal.Type: GrantFiled: June 9, 2014Date of Patent: October 20, 2015Assignee: XILINX, INC.Inventors: Anil Kumar Kandala, Srinivasa L. Karumajji, Vikram Santurkar