Abstract: Disclosed are novel methods and apparatus for efficiently providing equalization in single-ended chip-to-chip communication. In an embodiment, a method of adjusting signal levels to provide improved communication between a sender device and a receiver device is disclosed. The method includes providing a plurality of voltage dividers. The plurality of voltage dividers may be coupled to each other to provide a reference voltage to the receiver device. The method further includes providing a storage device to store previously received data by the receiver device and providing a controller to selectively activate the plurality of voltage dividers.

Abstract: In some embodiments, a chip with a transmitter having a transmitter driver is provided. Also provided is a general compensation circuit coupled to the transmitter to generally compensate the transmitter driver and a specific compensation circuit coupled to the transmitter driver to specifically compensate the transmitter driver. Other embodiments are disclosed and claimed herein.

Abstract: A technique for incorporating power information in a register transfer level design involves defining a module representing an integrated circuit block having its own power grid. The integrated circuit block, when in a power off mode effectuated by a deactivation of a clock signal to the integrated circuit, uses a device dependent on a power grid of an adjoining integrated circuit block to preserve output information from the integrated circuit block to the adjoining integrated circuit block.

Abstract: A data transmission update technique for use in a low power mode and/or a low activity mode of a computer system or a portion thereof is provided. When in the low power mode and/or the low activity mode, the technique initiates a testing of data transmissions, the results of which are used to adjust the timing of data receipt such that accurate and timely date communications are facilitated.

Abstract: A method and apparatus for regulating resonance in a computer system I/O interface is provided. A shunting impedance/resistance is arranged across a power supply of the I/O interface. The shunting impedance/resistance is controlled by circuitry that is arranged to detect voltage overshoot conditions in the I/O interface. The circuitry has (1) an analog front end that is arranged to detect power supply oscillations relative to a grounded terminal, (2) an amplifier (or logic conversion circuit) that is arranged to convert an output signal from the analog front end to a digital signal, and (3) a shunting apparatus arranged to modify power supply behavior in the I/O interface dependent on the digital signal.

Abstract: A delay locked loop implementing design-for-test features to test for, among other, stuck-at-faults is provided. The delay locked loop uses multiplexers as design-for-test devices for controllability purposes and flip-flops as design-for-test devices for observability purposes. Such implementation of design-for-test features within a delay locked loop allows for pre-packaging delay locked loop verification and testing.

Abstract: Disclosed are novel methods and apparatus for efficiently providing equalization in single-ended chip-to-chip communication. In an embodiment, a method of adjusting signal levels to provide improved communication between a sender device and a receiver device is disclosed. The method includes providing a plurality of voltage dividers. The plurality of voltage dividers may be coupled to each other to provide a reference voltage to the receiver device. The method further includes providing a storage device to store previously received data by the receiver device and providing a controller to selectively activate the plurality of voltage dividers.

Abstract: A source synchronous interface determines an amount of delay for an incoming data signal and a phase offset for a latch device that latches the incoming data signal. A delay locked loop may be a dual loop delay locked loop, in which case, the loops may use a low jitter, local clock signal and an input clock signal that was transmitted with the data signal. The low jitter, local clock signal may provide a stable source from which to derive good clock signal edge transitions. The input clock signal may be used to determine the long term clock signal drift. A finite state machine within the dual loop delay locked loop may provide the necessary information for the amount of delay and the phase offset. The delay of the incoming data signal is produced by a digital delay line.

Abstract: A technique for incorporating power information in a register transfer level design involves defining a module representing an integrated circuit block having its own power grid. The integrated circuit block, when in a power off mode effectuated by a deactivation of a clock signal to the integrated circuit, uses a device dependent on a power grid of an adjoining integrated circuit block to preserve output information from the integrated circuit block to the adjoining integrated circuit block.

Abstract: A data transmission update technique for use in a low power mode and/or a low activity mode of a computer system or a portion thereof is provided. When in the low power mode and/or the low activity mode, the technique initiates a testing of data transmissions, the results of which are used to adjust the timing of data receipt such that accurate and timely date communications are facilitated.

Abstract: A method and apparatus for regulating resonance in a computer system I/O interface is provided. A shunting impedance/resistance is arranged across a power supply of the I/O interface. The shunting impedance/resistance is controlled by circuitry that is arranged to detect voltage overshoot conditions in the I/O interface. The circuitry has (1) an analog front end that is arranged to detect power supply oscillations relative to a grounded terminal, (2) an amplifier (or logic conversion circuit) that is arranged to convert an output signal from the analog front end to a digital signal, and (3) a shunting apparatus arranged to modify power supply behavior in the I/O interface dependent on the digital signal.

Abstract: A source synchronous interface determines an amount of delay for an incoming data signal and a phase offset for a latch device that latches the incoming data signal. A delay locked loop may be a dual loop delay locked loop, in which case, the loops may use a low jitter, local clock signal and an input clock signal that was transmitted with the data signal. The low jitter, local clock signal may provide a stable source from which to derive good clock signal edge transitions. The input clock signal may be used to determine the long term clock signal drift. A finite state machine within the dual loop delay locked loop may provide the necessary information for the amount of delay and the phase offset. The delay of the incoming data signal is produced by an analog delay line.

Abstract: A source synchronous interface determines an amount of delay for an incoming data signal and a phase offset for a latch device that latches the incoming data signal. A delay locked loop may be a dual loop delay locked loop, in which case, the loops may use a low jitter, local clock signal and an input clock signal that was transmitted with the data signal. The low jitter, local clock signal may provide a stable source from which to derive good clock signal edge transitions. The input clock signal may be used to determine the long term clock signal drift. A finite state machine within the dual loop delay locked loop may provide the necessary information for the amount of delay and the phase offset. The delay of the incoming data signal is produced by a digital delay line.

Abstract: A delay locked loop implementing design-for-test features to test for, among other, stuck-at-faults is provided. The delay locked loop uses multiplexers as design-for-test devices for controllability purposes and flip-flops as design-for-test devices for observability purposes. Such implementation of design-for-test features within a delay locked loop allows for pre-packaging delay locked loop verification and testing.

Abstract: A method for reducing delay variability in a differential receiver includes receiving a plurality of differential input signals, determining a first transition delay time of an output in response to the plurality of differential input signals, determining a second transition delay time of the output in response to the plurality of differential input signals, and modifying capacitance coupled to the output in response to the first transition delay time and to the second transition delay time.

Abstract: A method for receiving data from a sending system in a receiving system includes receiving a pair of differential clock signals from the sending system, determining a reference voltage in the receiving system in response to the pair of differential clock signals, receiving a test data signal from the sending system, adjusting the reference voltage to form an updated reference voltage in response to the test data signal, receiving a single-ended data signal from the sending system relative to a reference voltage and determining a data signal in response to the single-ended data signal and to the updated reference voltage.

Abstract: The present invention is directed to an apparatus and method to clamp and terminate signals along a communication bus; the clamping and termination are performed dynamically whenever a signal exceeds a set peak value or falls below a set low value. Variations include a clamping and termination circuit made of metal oxide semiconductor (MOS) devices where one MOS device clamps for over-voltage and another MOS device clamps for under-voltage. Biasing circuits to the gates of the MOS devices assure that proper bias voltage is applied so that the MOS devices only clamp and terminate when a signal is received and that signal falls off the set high or low values, this assures dynamic clamping and termination and avoids unnecessary additional voltage from a driving device.