Abstract: Circuit techniques reduce or prevent audible artifacts in a Universal Audio Jack (UAJ) interface circuit, improving handling of mis-configuration/mis-attachment of devices. The interface includes at least one terminal for accepting an audio input signal or providing an audio line output signal coupled to an input or output of a first audio circuit. The first audio circuit operates from a low voltage domain and receives the audio input signal or provides the audio line output signal. A second circuit operates from a higher voltage domain and a switching circuit couples the at least one terminal to the second circuit. The output is slew-rate controlled to control a transition time of the output, so that audible artifacts in the audio input signal or the audio line output signal that could be generated by the switching circuit connecting the second circuit to the at least one terminal are avoided.

Abstract: Class D amplifier circuitry comprising: input buffer circuitry configured to receive a first digital input signal modulated according to a first modulation scheme in which the digital input signal can take a first plurality N of discrete signal levels; analog modulator circuitry configured to generate an analog modulated signal based on an analog output signal output by the input buffer circuitry; and quantizer circuitry configured to generate an output signal based on the analog modulated signal, wherein the output signal is modulated according to a second modulation scheme in which the output signal can take a second plurality M of discrete signal levels, wherein the second plurality M is greater than the first plurality N.

Abstract: A data acquisition system (DAS) for acquiring data from a Hall effect sensor includes one or more state variables, a multiplexer that periodically rotates a signal from the Hall effect sensor, and a controller that resets the one or more state variables in synchronization with rotation of the signal. The state variables may be digital states in a digital memory or voltages of capacitors the controller forces to a reset voltage. The state variables may be included in a noise-shaping SAR ADC, a delta-sigma ADC, a digital filter, an integrator, an analog filter, a VCO, an incremental ADC or an auxiliary ADC-assisted incremental ADC, or an auxiliary ADC of the DAS.

Abstract: Compositions and methods of using ILC2 to reduce microglial activation or to reduce blood-brain barrier (BBB) permeability are described. Also described are methods and compositions that use an agent that increases the number of activated ILC2 to reduce microglial activation or BBB permeability.

Abstract: A method and apparatus for detecting a microphone condition of a microphone, the method comprising: applying an electrical stimulus to a microphone; measuring an electrical response to the electrical stimulus at the microphone; comparing the electrical response to an expected response; and determining the microphone condition based on the comparison.

Abstract: Class D amplifier circuitry comprising: input buffer circuitry configured to receive a first digital input signal modulated according to a first modulation scheme in which the digital input signal can take a first plurality N of discrete signal levels; analog modulator circuitry configured to generate an analog modulated signal based on an analog output signal output by the input buffer circuitry; and quantizer circuitry configured to generate an output signal based on the analog modulated signal, wherein the output signal is modulated according to a second modulation scheme in which the output signal can take a second plurality M of discrete signal levels, wherein the second plurality M is greater than the first plurality N.

Abstract: A method and apparatus for detecting a microphone condition of a microphone, the method comprising: applying an electrical stimulus to a microphone; measuring an electrical response to the electrical stimulus at the microphone; comparing the electrical response to an expected response; and determining the microphone condition based on the comparison.

Abstract: The disclosure relates to methods of treating multiple sclerosis and maintaining or maximizing vaccine effectiveness. In certain aspects, the methods comprise administrating ponesimod, administering a vaccine, and interrupting the administration of the ponesimod.

Abstract: Digital-to-analog converter (DAC) architecture, comprising: a matrix DAC array comprising a plurality of cells arranged in a first dimension and a second dimension, each cell comprising a local decoder configured to transition the cell between at least two states; and decoding circuitry configured to: receive a digital input signal; and control the plurality of local decoders based on a received digital input signal, wherein each incremental change in the digital input signal results in a transition of a single cell of the plurality of cells such that the plurality of cells transition in sequence, the sequence of transitions of the plurality of cells defining a path through the DAC array; wherein when the path proceeds in the first dimension, the path proceeds to an adjacent cell of the plurality of cells at least 50% of the time; and wherein when the path proceeds in the second dimension, the path proceeds to an adjacent cell of the plurality of cells at least 50% of the time.

Abstract: The present disclosure describes a sequencing system configured to identify structural variants in mitochondrial DNA. Variant callers configured to identify variants in linear genomes (e.g., those found in chromosomes) can fail to properly identify structural variants in mitochondrial DNA. The system and methods can identify structural variants in next generation sequencing data collected from circular, mitochondrial DNA.

Abstract: A system may include a digitally-controlled oscillator configured to generate an output clock signal based on a control signal received at an input of the digitally-controlled oscillator and a control circuit configured to calculate an error signal between the output clock signal and an external reference clock signal, filter the error signal to generate a correction signal, generate the control signal based on the correction signal, and switch between a first mode of operation and a second mode of operation without artifacts on the correction signal during switching between the first mode and the second mode.

Abstract: A data acquisition system (DAS) for processing an input signal from a resistive sensor (e.g., Hall effect sensor) includes a sensor signal path that digitizes the input signal. An input impedance of the sensor signal path attenuates the input signal. A gain error corrector applies a gain error correction factor in a digital domain of the DAS to the digitized input signal to compensate for a loading effect to the resistive sensor. The sensor signal path includes an inverting amplifier that provides low distortion for the input signal and an ADC (e.g., delta-sigma, SAR, pipelined, auxiliary) that digitizes the input signal. A sensor characterization path digitizes the sensor resistance which the gain error corrector uses, along with the inverting amplifier input impedance, to calculate the gain error correction factor.

Abstract: A method and apparatus for detecting a microphone condition of a microphone, the method comprising: applying an electrical stimulus to a microphone; measuring an electrical response to the electrical stimulus at the microphone; comparing the electrical response to an expected response; and determining the microphone condition based on the comparison.

Abstract: A data acquisition system (DAS) for acquiring data from a Hall effect sensor includes one or more state variables, a multiplexer that periodically rotates a signal from the Hall effect sensor, and a controller that resets the one or more state variables in synchronization with rotation of the signal. The state variables may be digital states in a digital memory or voltages of capacitors the controller forces to a reset voltage. The state variables may be included in a noise-shaping SAR ADC, a delta-sigma ADC, a digital filter, an integrator, an analog filter, a VCO, an incremental ADC or an auxiliary ADC-assisted incremental ADC, or an auxiliary ADC of the DAS.

Abstract: A data acquisition system (DAS) for processing an input signal from a resistive sensor (e.g., Hall effect sensor) includes a sensor signal path that digitizes the input signal. An input impedance of the sensor signal path attenuates the input signal. A gain error corrector applies a gain error correction factor in a digital domain of the DAS to the digitized input signal to compensate for a loading effect to the resistive sensor. The sensor signal path includes an inverting amplifier that provides low distortion for the input signal and an ADC (e.g., delta-sigma, SAR, pipelined, auxiliary) that digitizes the input signal. A sensor characterization path digitizes the sensor resistance which the gain error corrector uses, along with the inverting amplifier input impedance, to calculate the gain error correction factor.

Abstract: The systems and methods discussed herein can calculate sequencing statistics such as coverage depth for sequencing data. The present solution can determine variant frequencies and identify clinically relevant variants. The present solution can read BAM and VCF input files and Phred scaled quality scores. The present solution can select relatively high quality reads based on the quality scores and can calculate reference and alternative allele counts for SNPs, insertions and deletions (INDELs), and structural variants.

Abstract: A selectable output current mirror may include a reference leg configured to generate a reference current, an output leg electrically coupled to the reference leg in a manner such that the output leg is configured to generate at an output of the output leg an output current proportional to the reference current, wherein the output leg comprises an output leg transistor, a drain path switch coupled between a first non-gate terminal of the output leg transistor and the output of the output leg, and a series combination of a degeneration resistor and a degeneration path switch coupled between a second non-gate terminal of the output leg transistor and a voltage source to the selectable output current mirror.

Abstract: A selectable output current mirror may include a reference leg configured to generate a reference current, an output leg electrically coupled to the reference leg in a manner such that the output leg is configured to generate at an output of the output leg an output current proportional to the reference current, wherein the output leg comprises an output leg transistor, a drain path switch coupled between a first non-gate terminal of the output leg transistor and the output of the output leg, and a series combination of a degeneration resistor and a degeneration path switch coupled between a second non-gate terminal of the output leg transistor and a voltage source to the selectable output current mirror.

Abstract: In accordance with embodiments of the present disclosure, an apparatus for measuring acceleration may include a spring-mounted mass, a positional encoder configured to measure a position of the spring-mounted mass and output one or more signals indicative of a sine and a cosine of the position, a driver to set and maintain an oscillation of the spring-mounted mass, and a decoder configured to process the one or more signals to calculate an acceleration of the spring-mounted mass.

Abstract: Compositions and methods of using ILC2 to reduce microglial activation or to reduce blood-brain barrier (BBB) permeability are described. Also described are methods and compositions that use an agent that increases the number of activated ILC2 to reduce microglial activation or BBB permeability.