Patents by Inventor Anish Khandekar

Anish Khandekar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11871582
    Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Hung-Wei Liu, Vassil N. Antonov, Ashonita A. Chavan, Darwin Franseda Fan, Jeffery B. Hull, Anish A. Khandekar, Masihhur R. Laskar, Albert Liao, Xue-Feng Lin, Manuj Nahar, Irina V. Vasilyeva
  • Patent number: 11805645
    Abstract: Some embodiments include a structure having an opening extending into an integrated configuration. A first material is within the opening, and is configured to create an undulating topography relative to a sidewall of the opening. The undulating topography has a surface roughness characterized by a mean roughness parameter Rmean which is the mean peak-to-valley distance along the undulating topography. The Rmean is at least about 4 nm. A second material is within the opening and along at least a portion of the undulating topography. The first and second materials are compositionally different from one another. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: October 31, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Nicholas R. Tapias, Andrew Li, Adam W. Saxler, Kunal Shrotri, Erik R. Byers, Matthew J. King, Diem Thy N. Tran, Wei Yeeng Ng, Anish A. Khandekar
  • Publication number: 20230307543
    Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 ?m3 of one another. Other embodiments, including methods, are disclosed.
    Type: Application
    Filed: May 10, 2023
    Publication date: September 28, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Hung-Wei Liu, Sameer Chhajed, Jeffery B. Hull, Anish A. Khandekar
  • Publication number: 20230276635
    Abstract: Methods, systems, and devices for on-die formation of single-crystal semiconductor structures are described. In some examples, a layer of semiconductor material may be deposited above one or more decks of memory cells and divided into a set of patches. A respective crystalline arrangement of each patch may be formed based on nearly or partially melting the semiconductor material, such that nucleation sites remain in the semiconductor material, from which respective crystalline arrangements may grow. Channel portions of transistors may be formed at least in part by doping regions of the crystalline arrangements of the semiconductor material. Accordingly, operation of the memory cells may be supported by lower circuitry (e.g., formed at least in part by doped portions of a crystalline semiconductor substrate), and upper circuitry (e.g., formed at least in part by doped portions of a semiconductor deposited over the memory cells and formed with a crystalline arrangement in-situ).
    Type: Application
    Filed: May 8, 2023
    Publication date: August 31, 2023
    Inventors: Jeffery Brandt Hull, Anish A. Khandekar, Hung-Wei Liu, Sameer Chhajed
  • Patent number: 11688808
    Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 ?m3 of one another. Other embodiments, including methods, are disclosed.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: June 27, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Hung-Wei Liu, Sameer Chhajed, Jeffery B. Hull, Anish A. Khandekar
  • Patent number: 11683937
    Abstract: Methods, systems, and devices for on-die formation of single-crystal semiconductor structures are described. In some examples, a layer of semiconductor material may be deposited above one or more decks of memory cells and divided into a set of patches. A respective crystalline arrangement of each patch may be formed based on nearly or partially melting the semiconductor material, such that nucleation sites remain in the semiconductor material, from which respective crystalline arrangements may grow. Channel portions of transistors may be formed at least in part by doping regions of the crystalline arrangements of the semiconductor material. Accordingly, operation of the memory cells may be supported by lower circuitry (e.g., formed at least in part by doped portions of a crystalline semiconductor substrate), and upper circuitry (e.g., formed at least in part by doped portions of a semiconductor deposited over the memory cells and formed with a crystalline arrangement in-situ).
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: June 20, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Jeffery Brandt Hull, Anish A. Khandekar, Hung-Wei Liu, Sameer Chhajed
  • Patent number: 11637175
    Abstract: A vertical transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The top source/drain region and the channel region have a top interface and the bottom source/drain region and the channel region have a bottom interface. The channel region is crystalline and has an average crystal grain size of its crystal grains that is less than 20 nanometers. The channel region at the top interface or at the bottom interface has greater horizontal texture than volume of the crystal grains in the channel region that is vertically between the crystal grains that are at the top and bottom interfaces. Other embodiments and aspects are disclosed.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: April 25, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Yi Fang Lee, Hung-Wei Liu, Ning Lu, Anish A. Khandekar, Jeffery B. Hull, Silvia Borsari
  • Patent number: 11621270
    Abstract: A method of forming polysilicon comprises forming a first polysilicon-comprising material over a substrate, with the first polysilicon-comprising material comprising at least one of elemental carbon and elemental nitrogen at a total of 0.1 to 20 atomic percent. A second polysilicon-comprising material is formed over the first polysilicon-comprising material. The second polysilicon-comprising material comprises less, if any, total elemental carbon and elemental nitrogen than the first polysilicon-comprising material. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: April 4, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Dimitrios Pavlopoulos, Kunal Shrotri, Anish A. Khandekar
  • Patent number: 11600494
    Abstract: A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: March 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Gordon A. Haller, Tom J. John, Anish A. Khandekar, Christopher Larsen, Kunal Shrotri
  • Publication number: 20230042701
    Abstract: Methods, systems, and devices for on-die formation of single-crystal semiconductor structures are described. In some examples, a layer of semiconductor material may be deposited above one or more decks of memory cells and divided into a set of patches. A respective crystalline arrangement of each patch may be formed based on nearly or partially melting the semiconductor material, such that nucleation sites remain in the semiconductor material, from which respective crystalline arrangements may grow. Channel portions of transistors may be formed at least in part by doping regions of the crystalline arrangements of the semiconductor material. Accordingly, operation of the memory cells may be supported by lower circuitry (e.g., formed at least in part by doped portions of a crystalline semiconductor substrate), and upper circuitry (e.g., formed at least in part by doped portions of a semiconductor deposited over the memory cells and formed with a crystalline arrangement in-situ).
    Type: Application
    Filed: August 9, 2021
    Publication date: February 9, 2023
    Inventors: Jeffery Brandt Hull, Anish A. Khandekar, Hung-Wei Liu, Sameer Chhajed
  • Patent number: 11469103
    Abstract: Methods, apparatuses, and systems related to semiconductor structure formation are described. An example method includes forming an opening through silicon (Si) material, formed over a semiconductor substrate, to a first depth to form pillars of Si material. The example method further includes depositing an isolation material within the opening to fill the opening between the Si pillars. The example method further includes removing a portion of the isolation material from between the pillars to a second depth to create a second opening between the pillars and defining inner sidewalls between the pillars. The example method further includes depositing an enhancer material over a top surface of the pillars and along the inner sidewalls of the pillars down to a top portion of the isolation material.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: October 11, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Nicholas R. Tapias, Sanjeev Sapra, Anish A. Khandekar, Shen Hu
  • Patent number: 11393688
    Abstract: Systems, methods and apparatus are provided for a semiconductor structure. An example method includes a method for forming a contact surface on a vertically oriented access devices. The method includes forming a first source/drain region and a second source/drain region vertically separated by a channel region, forming a sacrificial etch stop layer on a first side of the second source/drain region, wherein the channel region is in contact with a second side of the second source/drain region, forming a dielectric layer on a first side of the sacrificial etch stop layer, where the second source/drain region is connected to a second side of the sacrificial etch stop layer, removing the dielectric layer using a first etch process to expose the sacrificial etch stop layer, and removing the sacrificial etch stop layer using a second etch process to form a contact surface on the second source/drain region.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jerome A. Imonigie, Guangjun Yang, Anish A. Khandekar, Yoshitaka Nakamura, Yi Fang Lee
  • Patent number: 11387369
    Abstract: An example apparatus includes forming a working surface of a substrate material. The example apparatus includes trench formed between two semiconductor structures on the working surface of the substrate material. The example apparatus further includes access lines formed on neighboring sidewalls of the semiconductor structures opposing a channel region separating a first source/drain region and a second source/drain region. The example apparatus further includes a time-control formed inhibitor material formed over a portion of the sidewalls of the semiconductor structures. The example apparatus further includes a dielectric material formed over the semiconductor structures to enclose a non-solid space between the access lines.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: July 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Shen Hu, Hung-Wei Liu, Xiao Li, Zhiqiang Xie, Corey Staller, Jeffery B. Hull, Anish A. Khandekar, Thomas A. Figura
  • Publication number: 20220181434
    Abstract: A vertical transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The top source/drain region and the channel region have a top interface and the bottom source/drain region and the channel region have a bottom interface. The channel region is crystalline and has an average crystal grain size of its crystal grains that is less than 20 nanometers. The channel region at the top interface or at the bottom interface has greater horizontal texture than volume of the crystal grains in the channel region that is vertically between the crystal grains that are at the top and bottom interfaces. Other embodiments and aspects are disclosed.
    Type: Application
    Filed: December 9, 2020
    Publication date: June 9, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Yi Fang Lee, Hung-Wei Liu, Ning Lu, Anish A. Khandekar, Jeffery B. Hull, Silvia Borsari
  • Publication number: 20220157837
    Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.
    Type: Application
    Filed: January 31, 2022
    Publication date: May 19, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Hung-Wei Liu, Vassil N, Antonov, Ashonita A. Chavan, Darwin Franseda Fan, Jeffrey B. Hull, Anish A. Khandekar, Masihhur R. Laskar, Albert Liao, Xue-Feng Lin, Manuj Nahar, Irina V. Vasilyeva
  • Publication number: 20220093617
    Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.
    Type: Application
    Filed: September 21, 2020
    Publication date: March 24, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Hung-Wei Liu, Vassil N. Antonov, Ashonita A. Chavan, Darwin Franseda Fan, Jeffery B. Hull, Anish A. Khandekar, Masihhur R. Laskar, Albert Liao, Xue-Feng Lin, Manuj Nahar, Irina V. Vasilyeva
  • Patent number: 11264395
    Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: March 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Hung-Wei Liu, Vassil N. Antonov, Ashonita A. Chavan, Darwin Franseda Fan, Jeffery B. Hull, Anish A. Khandekar, Masihhur R. Laskar, Albert Liao, Xue-Feng Lin, Manuj Nahar, Irina V. Vasilyeva
  • Publication number: 20220045195
    Abstract: Systems, methods and apparatus are provided for a semiconductor structure. An example method includes a method for forming a contact surface on a vertically oriented access devices. The method includes forming a first source/drain region and a second source/drain region vertically separated by a channel region, forming a sacrificial etch stop layer on a first side of the second source/drain region, wherein the channel region is in contact with a second side of the second source/drain region, forming a dielectric layer on a first side of the sacrificial etch stop layer, where the second source/drain region is connected to a second side of the sacrificial etch stop layer, removing the dielectric layer using a first etch process to expose the sacrificial etch stop layer, and removing the sacrificial etch stop layer using a second etch process to form a contact surface on the second source/drain region.
    Type: Application
    Filed: August 4, 2020
    Publication date: February 10, 2022
    Inventors: Jerome A. Imonigie, Guangjun Yang, Anish A. Khandekar, Yoshitaka Nakamura, Yi Fang Lee
  • Publication number: 20210351197
    Abstract: A method of forming polysilicon comprises forming a first polysilicon-comprising material over a substrate, with the first polysilicon-comprising material comprising at least one of elemental carbon and elemental nitrogen at a total of 0.1 to 20 atomic percent. A second polysilicon-comprising material is formed over the first polysilicon-comprising material. The second polysilicon-comprising material comprises less, if any, total elemental carbon and elemental nitrogen than the first polysilicon-comprising material. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 11, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Dimitrios Pavlopoulos, Kunal Shrotri, Anish A. Khandekar
  • Publication number: 20210265502
    Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 ?m3 of one another. Other embodiments, including methods, are disclosed.
    Type: Application
    Filed: May 11, 2021
    Publication date: August 26, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Hung-Wei Liu, Sameer Chhajed, Jeffery B. Hull, Anish A. Khandekar