Patents by Inventor Anjna Khanna

Anjna Khanna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9305133
    Abstract: A system and method are provided for selective application and expeditious reconciliation of constraints within a hierarchy of circuit design constraints. A semi-transparent constraint editor user interface is provided in contextual registration near detected violations during editing interactions with a circuit design. The constraint editor provides a simplified representation of a lookup order of a hierarchy of constraints applicable to an object related to the detected violation. The user is then able to easily modify constrained values within the lookup order, modify the lookup order, or modify the editing interaction to reconcile the violation expeditiously all while maintaining context within the circuit design.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: April 5, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sandipan Ghosh, Anjna Khanna
  • Patent number: 9064063
    Abstract: Disclosed encompasses method, system, computer program product for implementing interactive checking of constraints. Various embodiments bridge schematic design environment and layout environment with a binder mapping process and utilize connectivity information from the schematic design to identify constraint violations early in the physical design stage. The method identifies or creates a layout and identifies or generates an object for a modification process. The method may take snapshot(s) of the design database or may use one or more logs for restoring the design database. The method then identifies or creates scratch pad(s) and performs modification process on the object to generate a change. The method uses scratch pad(s) and trigger(s) to perform constraint checking during the modification process to provide interactive feedback in response to the modification process before committing the change to the persistent database.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: June 23, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Henry Yu, Joshua Baudhuin, Regis Colwell, Harsh Deshmane, Elias L. Fallon, Sanjib Ghosh, Anjna Khanna, Yinnie Lee, Harindranath Parameswaran, Pardeep Juneja, Roland Ruehl, Simon Simonian, Hui Xu, Timothy Rosek
  • Patent number: 8694943
    Abstract: Disclosed are methods and systems for implementing constraint and connectivity aware physical designs. The method or system provides a connectivity-aware environment to implement electronic designs. For example, the method interactively determines whether an electronic design complies with various constraints by using connectivity information in a nearly real-time manner while the electronic design is being created in some embodiments. The method or system uses the connectivity information provided by a connectivity engine or specified by designers to present feedback to a user as to whether a newly created object or a newly modified object complies or violates certain relevant constraints in an interactive manner or in nearly real-time without having to perform such constraints checking in batch mode. The method further enables one to implement electronic designs by using connectivity information without performing extraction on layouts or rebuilding nets.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: April 8, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Henry Yu, Roland Ruehl, Elias L. Fallon, Regis Colwell, Joshua Baudhuin, Hui Xu, Harsh Deshmane, Yinnie Lee, Simon Simonian, Harindranath Parameswaran, Pardeep Juneja, Anjna Khanna, Sanjib Ghosh, Timothy Rosek