Patents by Inventor Ankireddy Nalamalpu

Ankireddy Nalamalpu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11070209
    Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: July 20, 2021
    Assignee: Intel Corporation
    Inventors: Dheeraj Subbareddy, Md Altaf Hossain, Ankireddy Nalamalpu, Robert Sankman, Ravindranath Mahajan, Gregg William Baeckler
  • Patent number: 11056452
    Abstract: An IC includes first, second, and third IOs, and a multiplexer that includes first and second inputs, and an output. The IC includes first and second transmitters respectively having an output coupled to the first IO and an output coupled to the second IO. A clock generator is coupled between the output and an input of the first transmitter and between the output and an input of the second transmitter. The first input may receive a clock signal generated by the first clock generator and the second clock input is coupled to the third IO and may receive a clock signal via the third IO element from another IC. An IC includes a programmable fabric, k*n wires coupled to and extending from the fabric, n TDMs, and n IO blocks. Each TDM includes k inputs coupled to k wires and an output coupled to one of the IO blocks.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Dheeraj Subbareddy, Ankireddy Nalamalpu, Md Altaf Hossain
  • Publication number: 20210066178
    Abstract: An integrated circuit package may include a semiconductor die on a first side of the integrated circuit package, a first ball grid array (BGA) connection on the first side of the integrated circuit package, and a second BGA connection on a second side of the integrated circuit package. The integrated circuit package may include one or more traces that route data from the first BGA connection and the second BGA connection.
    Type: Application
    Filed: November 13, 2020
    Publication date: March 4, 2021
    Inventors: MD Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy, Dinesh Somasekhar
  • Publication number: 20210013887
    Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.
    Type: Application
    Filed: September 25, 2020
    Publication date: January 14, 2021
    Inventors: Sharath Raghava, Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad, Sean R. Atsatt
  • Publication number: 20200402937
    Abstract: An integrated circuit package may be formed comprising an interposer with a center die and a plurality of identical integrated circuit dice positioned around the center die and attached to the interposer, wherein the center die is the switch/router for the plurality of identical integrated circuit dice. The interposer comprises a substrate, a central pattern of bond pads formed in or on the substrate for attaching the center die, and substantially identical satellite patterns formed in or on the substrate for attaching identical integrated circuit dice. The central pattern of bond pads has repeating sets of a specific geometric pattern and wherein the identical satellite patterns of bond pads are positioned to form the same geometric pattern as the specific geometric pattern of the central pattern of bond pads. Thus, substantially identical conductive routes may be formed between the center die and each of the identical integrated circuit dice.
    Type: Application
    Filed: June 24, 2019
    Publication date: December 24, 2020
    Applicant: Intel Corporation
    Inventors: Robert Sankman, Dheeraj Subbareddy, Md Altaf Hossain, Ankireddy Nalamalpu
  • Publication number: 20200357721
    Abstract: An integrated circuit structure that includes a first integrated circuit package and a second integrated circuit package is described. The two packages can be stacked above, for example, a printed circuit board. The top package is inverted, such that a first die of that top package is facing a second die of the bottom package. A cooling arrangement is in a gap between the first and second integrated circuit packages, and is thermally coupled to the first and second die. The cooling arrangement is to transfer heat generated by a first die of the first integrated circuit package and a second die of the second integrated circuit package. In some cases, structures comprising electrically conductive material (e.g., metal) are encapsulated by a molding compound or insulator, and extend between a first substrate of the first integrated circuit package and a second substrate of the second integrated circuit package.
    Type: Application
    Filed: May 9, 2019
    Publication date: November 12, 2020
    Applicant: Intel Corporation
    Inventors: Robert Sankman, MD Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy
  • Publication number: 20200321964
    Abstract: Systems and methods related to multi-die integrated circuits that may include dies having high-speed core interconnects. The high-speed core interconnects may be used to directly connect two adjacent dies.
    Type: Application
    Filed: May 22, 2020
    Publication date: October 8, 2020
    Inventors: Lai Guan Tang, Ankireddy Nalamalpu, Dheeraj Subbareddy
  • Patent number: 10790827
    Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Sharath Raghava, Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad, Sean R. Atsatt
  • Publication number: 20200226313
    Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.
    Type: Application
    Filed: March 27, 2020
    Publication date: July 16, 2020
    Inventors: Chee Hak Teh, Ankireddy Nalamalpu, MD Altaf Hossain, Dheeraj Subbareddy, Sean R. Atsatt, Lai Guan Tang
  • Publication number: 20200211969
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: MD Altaf HOSSAIN, Ankireddy NALAMALPU, Dheeraj SUBBAREDDY, Robert SANKMAN, Ravindranath V. MAHAJAN, Debendra MALLIK, Ram S. VISWANATH, Sandeep B. SANE, Sriram SRINIVASAN, Rajat AGARWAL, Aravind DASU, Scott WEBER, Ravi GUTALA
  • Publication number: 20200186149
    Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.
    Type: Application
    Filed: February 12, 2020
    Publication date: June 11, 2020
    Applicant: Intel Corporation
    Inventors: Dheeraj Subbareddy, MD Altaf Hossain, Ankireddy Nalamalpu, Robert Sankman, Ravindranath Mahajan, Gregg William Baeckler
  • Patent number: 10666261
    Abstract: Systems and methods related to multi-die integrated circuits that may include dies having high-speed core interconnects. The high-speed core interconnects may be used to directly connect two adjacent dies.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Lai Guan Tang, Ankireddy Nalamalpu, Dheeraj Subbareddy
  • Patent number: 10649927
    Abstract: A central processing unit (CPU) may be directly coupled to an accelerator dual in-line memory module (DIMM) card that is plugged into a DIMM slot. The CPU may include a master memory controller that sends requests or offloads tasks to the accelerator DIMM card via a low-latency double data rate (DDR) interface. The acceleration DIMM card may include a slave memory controller for translating the received requests, a decoder for decoding the translated requests, control circuitry for orchestrating the data flow within the DIMM card, hardware acceleration resources that can be dynamically programmed to support a wide variety of custom functions, and input-output components for interfacing with various types of non-volatile and/or volatile memory and for connecting with other types of storage and processing devices.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Sharath Raghava, Dheeraj Subbareddy, Kavitha Prasad, Ankireddy Nalamalpu, Harsha Gupta
  • Publication number: 20200144186
    Abstract: A package substrate and a package assembly including a package substrate including a substrate body including a plurality of first contact points on a surface thereof configured for electrical connection to a first die and a plurality of second contact points on the surface configured for electrical connection to a second die; and a bridge coupled to the substrate body, the bridge including active device circuitry that is coupled to ones of the plurality of first contact points and ones of the plurality of second contact points. A method of forming a package assembly including coupling a first die to a package substrate, the package substrate including a bridge substrate including active device circuitry; and coupling a second die to the package substrate, wherein coupling the first die and the second die to the package substrate includes coupling the first die and the second die to the active circuitry.
    Type: Application
    Filed: September 13, 2017
    Publication date: May 7, 2020
    Inventors: Thomas P. THOMAS, Wilfred GOMES, Ravindranath V. MAHAJAN, Rajesh KUMAR, Mark T. BOHR, Dheeraj SUBBAREDDY, Ankireddy NALAMALPU, Mahesh KUMASHIKAR
  • Patent number: 10642946
    Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Chee Hak Teh, Ankireddy Nalamalpu, Md Altaf Hossain, Dheeraj Subbareddy, Sean R. Atsatt, Lai Guan Tang
  • Publication number: 20200133902
    Abstract: Systems and method include one or more die coupled to an interposer. The interposer includes interconnection circuitry configured to electrically connect the one or more die together via the interposer. The interposer also includes translation circuitry configured to translate communications as they pass through the interposer. For instance, in the interposer, the translation circuitry translates communications, in the interposer, from a first protocol of a first die of the one or more die to a second protocol of a second die of the one or more die.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 30, 2020
    Inventors: Lai Guan Tang, Ankireddy Nalamalpu, Dheeraj Subbareddy, Chee Hak Teh, MD Altaf Hossain
  • Patent number: 10601426
    Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventors: Dheeraj Subbareddy, Md Altaf Hossain, Ankireddy Nalamalpu, Robert Sankman, Ravindranath Mahajan, Gregg William Baeckler
  • Publication number: 20200083890
    Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.
    Type: Application
    Filed: September 6, 2018
    Publication date: March 12, 2020
    Applicant: Intel Corporation
    Inventors: Dheeraj Subbareddy, MD Altaf Hossain, Ankireddy Nalamalpu, Robert Sankman, Ravindranath Mahajan, Gregg William Baeckler
  • Publication number: 20200006175
    Abstract: A multi-chip packaged device may include a first integrated circuit die with a first integrated circuit, such that the first integrated circuit may include a first plurality of ports disposed on a first side and a second plurality of ports disposed on a second side of the first integrated circuit die. The multi-chip packaged device may also include a second integrated circuit die, such that the second integrated circuit may include a third plurality of ports disposed on a third side of the second integrated circuit die. The first integrated circuit may communicate with the first side of the second integrated circuit when placed adjacent to the first side and communicate with the second side of the first integrated circuit die when placed adjacent to the second side.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy
  • Publication number: 20190333854
    Abstract: An electronic chip, system, and method includes a power block including a power source configured to provide power to components of the electronic chip and a relay circuit coupled to the power source and a ground plane. The electronic chip further includes chip package having a first major side and a second major side, the power block secured to the second major side, the chip package comprising electrical connections, disposed on the second major side, to be secured with respect to a circuit board, and interconnect circuitry, electrically coupling the power block to ground, comprising a plurality of conductive layers, a conductive through hole, electrically connecting a first pair of the plurality of conductive layers, having a first width, and a via, electrically connecting a second pair of the plurality of conductive layers, having a second width less than the first width.
    Type: Application
    Filed: December 30, 2016
    Publication date: October 31, 2019
    Inventors: MD Altaf Hossain, Ankireddy Nalamalpu, Scott Gilbert, Jin Zhao