Patents by Inventor Ankireddy Nalamalpu

Ankireddy Nalamalpu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12153866
    Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: November 26, 2024
    Assignee: Altera Corporation
    Inventors: Chee Hak Teh, Ankireddy Nalamalpu, MD Altaf Hossain, Dheeraj Subbareddy, Sean R. Atsatt, Lai Guan Tang
  • Publication number: 20240348253
    Abstract: Systems or methods of the present disclosure may provide an integrated circuit device that implements one region definition, which may decrease design complexity, decrease software complexity, and increase ease of use. For example, the integrated circuit device may include programmable logic that implements one region definition. The region definition may include circuitry that may implement three-dimensional (3D) input/output circuitry, 2.5D input/output circuitry, circuitry for intra-die communication, circuitry for inter-package communication, or any combination thereof. By implementing one region definition on the integrated circuit device, time spent defining each programmable logic region may be reduced or eliminated, thereby reducing design complexity software complexity associated with the integrated circuit device.
    Type: Application
    Filed: June 27, 2024
    Publication date: October 17, 2024
    Inventors: Atul Maheshwari, Mahesh K. Kumashikar, MD Altaf Hossain, Ankireddy Nalamalpu, Krishna Bharath Kolluru, Jeffrey Christopher Chromczak
  • Publication number: 20240346224
    Abstract: Systems or methods of the present disclosure may provide a multi-chip package with two or more integrated circuit devices that each include hybrid bumps. The hybrid bumps may include bumps of different sizes to facilitate different types of communication. For example, the hybrid bumps may include a first bump with fine pitch for die-to-die communication and/or a second bump with a large pitch for off-package communication. The multi-chip package may include a bridge to facilitate signal transfer between the integrated circuit device with the hybrid bumps and other components within the multi-chip package. Additionally or alternatively, the multi-chip package may include an interconnect to facilitate signal transfer between two integrated circuit devices. The interconnect may include fine pitch bumps, which may be translated by an interposer to a pitch size of the bridge. As such, the interconnect may facilitate die-to-die communication and/or off-package communication.
    Type: Application
    Filed: June 27, 2024
    Publication date: October 17, 2024
    Inventors: Mahesh K. Kumashikar, Atul Maheshwari, MD Altaf Hossain, Ankireddy Nalamalpu, Krishna Bharath Kolluru
  • Publication number: 20240321716
    Abstract: An electronic device includes conductive pads that are formed on a surface of the electronic device. Each of the conductive pads has an oval shape. The conductive pads are coupled to deliver at least one of a power supply voltage or a ground voltage between an external device and the electronic device.
    Type: Application
    Filed: May 31, 2024
    Publication date: September 26, 2024
    Applicant: Altera Corporation
    Inventors: Md Altaf Hossain, Atul Maheshwari, Mahesh Kumashikar, Ankireddy Nalamalpu, Krishna Bharath Kolluru
  • Publication number: 20240321670
    Abstract: An electronic device includes a first layer and a thermal heatsink that comprises a conductive region in a second layer of the electronic device. The thermal heatsink further comprises a first via that extends through the first layer. The first via is filled with conductive material that is coupled to the conductive region. The conductive material in the first via is coupled to an external terminal of the electronic device. The electronic device can also include a second via filled with conductive material that is coupled to the conductive region.
    Type: Application
    Filed: May 30, 2024
    Publication date: September 26, 2024
    Applicant: Altera Corporation
    Inventors: Atul Maheshwari, Mahesh Kumashikar, Md Altaf Hossain, Ankireddy Nalamalpu, Ritochit Chakraborty, Krishna Bharath Kolluru
  • Publication number: 20240312905
    Abstract: An integrated circuit package includes first and second integrated circuit dies stacked vertically and coupled together, a connection device coupled to the first integrated circuit die, and a power delivery device coupled to the connection device. The power delivery device includes an inductor. The inductor generates supply current. The inductor is coupled to provide the supply current from the inductor to the first integrated circuit die through the connection device.
    Type: Application
    Filed: May 29, 2024
    Publication date: September 19, 2024
    Applicant: Altera Corporation
    Inventors: Md Altaf Hossain, Atul Maheshwari, Mahesh Kumashikar, Ankireddy Nalamalpu, Krishna Bharath Kolluru
  • Patent number: 12038858
    Abstract: A processor package module comprises a substrate, one or more compute die mounted to the substrate, and one or more photonic die mounted to the substrate. The photonic die have N optical I/O links to transmit and receive optical I/O signals using a plurality of virtual optical channels, the N optical I/O links corresponding to different types of I/O interfaces excluding power and ground I/O. The substrate is mounted into a socket that support the power and ground I/O and electrical connections between the one or more compute die and the one or more photonic die.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: July 16, 2024
    Assignee: Intel Corporation
    Inventors: Anshuman Thakur, Dheeraj Subareddy, Md Altaf Hossain, Ankireddy Nalamalpu, Mahesh Kumashikar, Sandeep Sane
  • Patent number: 12026008
    Abstract: An integrated circuit die includes input buffer circuits that are enabled during an input mode of operation in response to first control signals to transmit input signals into the integrated circuit die from conductive bumps. Each of the input buffer circuits is coupled to one of the conductive bumps. The integrated circuit die also includes output buffer circuits that are each coupled to one of the conductive bumps. The output buffer circuits are enabled during an output mode of operation in response to second control signals to transmit output signals from the integrated circuit die to the conductive bumps. The input buffer circuits are disabled from transmitting signals during the output mode of operation in response to the first control signals. The output buffer circuits are disabled from transmitting signals during the input mode of operation in response to the second control signals.
    Type: Grant
    Filed: October 25, 2022
    Date of Patent: July 2, 2024
    Assignee: Altera Corporation
    Inventors: Jeffrey Chromczak, Chooi Pei Lim, Lai Guan Tang, Chee Hak Teh, MD Altaf Hossain, Dheeraj Subbareddy, Ankireddy Nalamalpu
  • Publication number: 20240213201
    Abstract: An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.
    Type: Application
    Filed: March 7, 2024
    Publication date: June 27, 2024
    Inventors: MD Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy
  • Patent number: 12007929
    Abstract: A processor having a system on a chip (SOC) architecture comprises one or more central processing units (CPUs) comprising multiple cores. An optical Compute Express Link (CXL) communication path incorporating a logical optical CXL protocol stack path transmits and receives an optical bit stream directly after the link layer, bypassing multiple levels of the CXL protocol stack. A CXL interface controller is connected to the one or more CPUs to enable communication between the CPUs and one or more CXL devices over the optical CXL communication path.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: June 11, 2024
    Assignee: Altera Corporation
    Inventors: Anshuman Thakur, Dheeraj Subbareddy, MD Altaf Hossain, Ankireddy Nalamalpu, Mahesh Kumashikar
  • Patent number: 11983135
    Abstract: Embodiments herein relate to systems, apparatuses, or processes for improving off-package edge bandwidth by overlapping electrical and optical serialization/deserialization (SERDES) interfaces on an edge of the package. In other implementations, off-package bandwidth for a particular edge of a package may use both an optical fanout and an electrical fanout on the same edge of the package. In embodiments, the optical fanout may use a top surface or side edge of a die and the electrical fanout may use the bottom side edge of the die. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: May 14, 2024
    Assignee: Intel Corporation
    Inventors: Dheeraj Subbareddy, Ankireddy Nalamalpu, Anshuman Thakur, Md Altaf Hossain, Mahesh Kumashikar, Kemal Aygün, Casey Thielen, Daniel Klowden, Sandeep B. Sane
  • Publication number: 20240145395
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 2, 2024
    Inventors: MD Altaf HOSSAIN, Ankireddy NALAMALPU, Dheeraj SUBBAREDDY, Robert SANKMAN, Ravindranath V. MAHAJAN, Debendra MALLIK, Ram S. VISWANATH, Sandeep B. SANE, Sriram SRINIVASAN, Rajat AGARWAL, Aravind DASU, Scott WEBER, Ravi GUTALA
  • Publication number: 20240145434
    Abstract: Die configuration types are provided that may be used together with other instances of the design to create multi die modules.
    Type: Application
    Filed: June 16, 2023
    Publication date: May 2, 2024
    Inventors: Mahesh KUMASHIKAR, MD Altaf HOSSAIN, Ankireddy NALAMALPU
  • Publication number: 20240120302
    Abstract: An electronic device includes first and second external conductive pads coupled to route a first signal and third and fourth external conductive pads. The third and the fourth external conductive pads are between the first and the second external conductive pads on a surface of the electronic device.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 11, 2024
    Applicant: Intel Corporation
    Inventors: Krishna Bharath Kolluru, Atul Maheshwari, Mahesh Kumashikar, Md Altaf Hossain, Ankireddy Nalamalpu, Omkar Karhade
  • Publication number: 20240113014
    Abstract: An integrated circuit includes first external conductive pads, second external conductive pads, and third external conductive pads. The second external conductive pads are between the first external conductive pads and the third external conductive pads. Repair group circuitry is configurable to shift signal transmission away from one of the first external conductive pads to one of the third external conductive pads if the one of the first external conductive pads has a defect.
    Type: Application
    Filed: December 13, 2023
    Publication date: April 4, 2024
    Applicant: Altera Corporation
    Inventors: Krishna Bharath Kolluru, Atul Maheshwari, Mahesh Kumashikar, Md Altaf Hossain, Ankireddy Nalamalpu, Jeffrey Chromczak
  • Publication number: 20240111703
    Abstract: An active interconnection device has a repeater circuit that includes a storage circuit. The storage circuit is coupled to store a configuration bit for configuring the repeater circuit to transmit a signal between a first integrated circuit die and a second integrated circuit die. The storage circuit is coupled to receive the configuration bit through a conductor during a configuration mode. A buffer circuit in the repeater circuit is configurable to transmit the signal through the conductor during a transmission mode in response to the configuration bit.
    Type: Application
    Filed: December 12, 2023
    Publication date: April 4, 2024
    Applicant: Altera Corporation
    Inventors: Mahesh Kumashikar, Atul Maheshwari, Md Altaf Hossain, Ankireddy Nalamalpu, Krishna Bharath Kolluru
  • Publication number: 20240096810
    Abstract: A circuit system includes a support device having an interconnection conductor. The circuit system also includes first, second, and third integrated circuits that are mounted on the support device. The interconnection conductor couples the first integrated circuit to the third integrated circuit. The second integrated circuit is between the first integrated circuit and the third integrated circuit.
    Type: Application
    Filed: June 7, 2023
    Publication date: March 21, 2024
    Applicant: Intel Corporation
    Inventors: Md Altaf Hossain, Mahesh Kumashikar, Ankireddy Nalamalpu
  • Patent number: 11929339
    Abstract: An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Md Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy
  • Patent number: 11915996
    Abstract: An integrated circuit structure that includes a first integrated circuit package and a second integrated circuit package is described. The two packages can be stacked above, for example, a printed circuit board. The top package is inverted, such that a first die of that top package is facing a second die of the bottom package. A cooling arrangement is in a gap between the first and second integrated circuit packages, and is thermally coupled to the first and second die. The cooling arrangement is to transfer heat generated by a first die of the first integrated circuit package and a second die of the second integrated circuit package. In some cases, structures comprising electrically conductive material (e.g., metal) are encapsulated by a molding compound or insulator, and extend between a first substrate of the first integrated circuit package and a second substrate of the second integrated circuit package.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: February 27, 2024
    Assignee: Intel Corporation
    Inventors: Robert Sankman, Md Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy
  • Patent number: 11901299
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: February 13, 2024
    Assignee: Intel Corporation
    Inventors: Md Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy, Robert Sankman, Ravindranath V. Mahajan, Debendra Mallik, Ram S. Viswanath, Sandeep B. Sane, Sriram Srinivasan, Rajat Agarwal, Aravind Dasu, Scott Weber, Ravi Gutala