Abstract: A device including a system phase lock loop circuit to: receive a primary reference clock, generate a reference clock from the primary reference clock, and transmit the reference clock; and a phase lock loop circuit to receive the reference clocks, generate a sub-reference clock from the received respective reference clocks, and transmit the sub-reference clock from the phase lock loop circuit to drive operation of a first chiplet using the respective sub-reference clock, wherein the sub-reference clock drives the first chiplet.

Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

Abstract: A method of handling integrated circuit dies with defects is provided. After forming a plurality of dies on one or more silicon wafers, test equipment may be used to identify defects on the dies and to create corresponding defect maps. The defect maps can be combined to form an aggregate defect map. Circuit design tools may create keep-out zones from the aggregate defect map and run learning experiments on each die, while respecting the keep-out zones, to compute design metrics. The circuit design tools may further create larger keep-out zones and run additional learning experiments on each die while respecting the larger keep-out zones to compute additional design metrics. The dies can be binned into different Stock Keeping Units (SKUs) based on one or more of the computed design metrics. Circuit design tools automatically respect the keep-out regions for these dies to program them correctly in the field.

Abstract: A multi-chip packaged device may include a first integrated circuit die with a first integrated circuit, such that the first integrated circuit may include a first plurality of ports disposed on a first side and a second plurality of ports disposed on a second side of the first integrated circuit die. The multi-chip packaged device may also include a second integrated circuit die, such that the second integrated circuit may include a third plurality of ports disposed on a third side of the second integrated circuit die. The first integrated circuit may communicate with the first side of the second integrated circuit when placed adjacent to the first side and communicate with the second side of the first integrated circuit die when placed adjacent to the second side.

Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.

Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.

Abstract: Embodiments of the present disclosure are related to dynamically adjusting a timing and/or power model for a programmable logic device. In particular, the present disclosure is directed to adjusting a timing and/or power model of the programmable logic device that operates at a voltage level that is not other than a predefined voltage defined by a voltage library. A system of the present disclosure may interpolate between voltage levels defined by the voltage libraries to generate a new voltage library for the programmable logic device. A timing and/or power model may be generated for the programmable logic device based on the new voltage library and the programmable logic device may be analyzed using the timing and/or power model at the interpolated voltage. The timing and/or power model may be used to generate a bitstream that is used to program the integrated circuit.

Abstract: A reticle-stitched integrated circuit is provided. The reticle-stitched integrated circuit extends over a first die area and a second die area of an integrated circuit wafer. While individually the first die area and the second die area are within their respective reticle limits, collectively the first die area and the second die area exceed the reticle limit. A first layer of the reticle-stitched integrated circuit may have communication wires that remain exclusively in only one of the first die area and the second die area. A second layer of the reticle-stitched integrated circuit may have communication wires that overlap the first die area and the second die area, thereby allowing communication between the two die areas and enabling the reticle-stitched integrated circuit to exceed the limit of the reticle.

Abstract: Systems or methods of the present disclosure may provide for operating a programmable fabric including multiple programmable elements organized into a number of power domains that utilize a common voltage within the respective power domains. A current sensor senses a current of the programmable fabric. When the sensed current has crossed a threshold, the programmable fabric changes the number of power domains.

Abstract: An integrated circuit device that includes programmable logic circuitry that includes a plurality of regions each configured to operate at different voltage levels. The regions may be separated by level shifters that enable communication between the different voltage level regions. The integrated circuitry may also include software that performs voltage aware placement and routing for a user register-transfer level design, and may direct logic to regions according to voltages defined for the regions.

Abstract: Systems or methods described herein may relate to latch-independent clock gating techniques to enable or disable an internal clock of an integrated circuit device. A programmable logic device includes a clock gating circuit that receives a clock signal and is latch independent. The clock gating circuit includes gating signal circuitry that generates a gating signal based on the clock signal and an enable signal. The clock gating circuit also includes a logic gate that generates a control signal based on the gating signal. The clock gating circuit also includes gated clock generation circuitry that generates a gated clock signal based on the clock signal and the control signal.

Abstract: Systems or methods of the present disclosure may provide efficient electric power consumption of programmable logic devices based on providing different voltage levels to different portions (e.g., voltage islands) of the programmable logic device. For example, the programmable logic device may include circuitry to provide different voltage levels to different voltage islands. The programmable logic device may implement and operate logic configurations with different operating parameters using different operating voltages for efficient electric power consumption.

Abstract: A processor package module comprises a substrate, one or more compute die mounted to the substrate, and one or more photonic die mounted to the substrate. The photonic die have N optical I/O links to transmit and receive optical I/O signals using a plurality of virtual optical channels, the N optical I/O links corresponding to different types of I/O interfaces excluding power and ground I/O. The substrate is mounted into a socket that support the power and ground I/O and electrical connections between the one or more compute die and the one or more photonic die.

Abstract: The present disclosure describes programmable logic that may be operated in a turbo processing mode to cause an ongoing operation to be completed faster than a scheduled completion time. With at least some of the remaining time to the scheduled completion time, power savings may be realized by operating the programmable logic into a deep sleep mode, where configuration memory associated with the programmable logic may be set to a suitable voltage level as to not cause data loss at lower or zero voltage levels but otherwise realize power savings relative to an amount of power consumed during average processing operations.

Abstract: A processor having a system on a chip (SOC) architecture comprises one or more central processing units (CPUs) comprising multiple cores. An optical Compute Express Link (CXL) communication path incorporating a logical optical CXL protocol stack path transmits and receives an optical bit stream directly after the link layer, bypassing multiple levels of the CXL protocol stack. A CXL interface controller is connected to the one or more CPUs to enable communication between the CPUs and one or more CXL devices over the optical CXL communication path.

Abstract: Systems or methods of the present disclosure may provide for determining a loadline for operation of a programmable logic fabric where the loadline is based at least in part on design configuration details for a design or a configuration rather for generic deployment of the programmable logic device. The loadline may be determined using software modeling for the design or configuration. Additionally or alternatively, the loadline may be determined using runtime testing and sensing of real-world parameters. This determination based on real-world parameters of a deployment of the configuration or design is based on a determination of a step load for the design or configuration.

Abstract: Systems or methods of the present disclosure may provide a programmable logic device including multiple logic array blocks each having multiple programmable elements. The multiple logic array blocks are arranged in multiple rows that are segmented into multiple segments. The programmable logic device also includes repair circuitry disposed between the multiple segments. The repair circuitry remaps logic within a first segment of the multiple segments when a first logic array block of the multiple logic array blocks has failed. Moreover, the first segment includes the first logic array block.

Abstract: Systems or methods of the present disclosure may provide for gradually adjusting a frequency of a clock signal. When transitioning from a configuration mode to a user mode, a clock of an integrated circuit (e.g., a field-programmable gate array or FPGA) may quickly (e.g., instantaneously) switch from a low configuration mode frequency to a high user mode frequency. This rapid increase in clock frequency may cause an inrush current and corresponding current-resistance voltage (IR) drop. To reduce or avoid the inrush current and IR drop, a frequency of the clock may be gradually ramped up from the configuration mode frequency to the user mode frequency.

Abstract: Systems or methods of the present disclosure may provide efficient power consumption for programmable logic devices based on reducing guardband voltages. A programmable logic device may include circuit monitors to mimic critical paths of an implemented circuit design and generate timing information based on the critical paths. A controller on the programmable logic device may adjust the voltage guardband based on the timing information.

Abstract: A digitally communicative circuit may use standardized interfaces for connection and communication with other circuit components. Such digitally communicative circuit may benefit from using wider variety of interconnect schemes with the respective interfaces for transmission and reception of data. Some chiplets may communicate using a high data bandwidth interface while other chiplets may communicate using interfaces with lower data bandwidth. Alternate interface is introduced that may facilitate scaled communication with Advanced Interface Bus 2.0 without translation circuitry and with different data bandwidth.