Abstract: Systems and methods are provided for simulating an integrated circuit system. A file representative of an integrated circuit layout is received, the integrated circuit layout including a plurality of cells and characteristics of power supply and ground paths to each cell. A vulnerable cell of the integrated circuit layout based on a vulnerability characteristic of the vulnerable cell. A power analysis of a portion of the integrated circuit layout is performed to determine a plurality of power and ground levels within a timing window for each of a plurality of cells including the vulnerable cell. A timing analysis of the vulnerable cell is performed, where the timing analysis receives a single power level and single ground level for the vulnerable cell and determines a slack level for the vulnerable cell. An at risk path is identified based on the vulnerable cell slack level, and a dynamic power/ground simulation of one or more cells in the at risk path is performed.

Abstract: A method and system for evaluating physiological properties of a segment of blood vessel is provided. The method includes: acquiring a first measurement and a second measurement respectively at the first point and the second point; obtaining a transfer function configured to produce an output given an input, using the first measurement and the second measurement as the input and the output respectively; and determining the physiological properties of the section of the blood vessel based on the transfer function. The transfer function can be a velocity transfer function based on the blood velocity waveforms, or can be a pressure transfer function based on the blood pressure waveforms. The method and system can be used to non-invasively diagnose PH, COPD, and PA impedance in a pulmonary artery, and to detect a stenosis in a coronary artery.

Abstract: A system and method for a master platform includes receiving first pose data associated with an image sensor of a first device, and a first semantic map generated by the first device, the first semantic map including a simplified object representation in a coordinate space of the first device. The master platform also receives second pose data associated with an image sensor of a second device, and a second semantic map generated by the second device, the second semantic map including a simplified object representation in a coordinate space of the second device. A shared simplified object representation common to the first and semantic maps is identified. The master platform further combines the first semantic and second semantic maps based on the first and second pose data. The first pose data, first semantic map, second pose data, and second semantic map are associated with a common time interval.

Abstract: Systems and methods are provided for simulating an integrated circuit system. A file representative of an integrated circuit design is received, the integrated circuit design including a plurality of cells and characteristics of power supply and ground paths to each cell. A vulnerable cell of the integrated circuit design based on a vulnerability metric of the vulnerable cell. A power analysis of a portion of the integrated circuit design is performed to determine a plurality of power and ground levels within a timing window for each of a plurality of cells including the vulnerable cell. A timing analysis of the vulnerable cell is performed, where the timing analysis receives a single power level and single ground level for the vulnerable cell and determines a slack level for the vulnerable cell. An at risk path is identified based on the vulnerable cell slack level, and a dynamic power/ground simulation of one or more cells in the at risk path is performed.

Abstract: A system for determining and tracking camera pose includes a dynamic vision sensor (DVS) configured to generate a current DVS image, an inertial measurement unit (IMU) configured to generate inertial data, and a memory. The memory is configured to store a 3-dimensional (3D) map of a known 3D environment. The system may also include a processor coupled to the memory. The processor is configured to initiate operations including determining a current camera pose for the DVS based on the current DVS image, the inertial data, the 3D map, and a prior camera pose.

Abstract: An apparatus includes a dynamic vision sensor (DVS) configured to output an asynchronous stream of sensor event data, a CMOS image sensor configured to output frames of image data, an inertial measurement unit (IMU), a processor and a memory. The memory contains instructions, which when executed by the processor, cause the apparatus to generate a semantic segmentation of a time-stamped frame, which is based on one or more of an output of the CMOS image sensor, or a synthesized event frame based on an output from the DVS and an output from the IMU over a time interval. The semantic segmentation includes a semantic label associated with a region of the time-stamped frame. When executed, the instructions further cause the apparatus to determine, based on the semantic segmentation, a simplified object representation in a coordinate space, and update a stable semantic map based on the simplified object representation.

Abstract: A computer implemented method for generating digital models of relative crop yield based on nitrate values in the soil is provided. In an embodiment, nitrate measurements from soil during a particular portion of a crop's development and corresponding crop yields are received by an agricultural intelligence computing system. Based, at least in part, on the nitrate measurements and corresponding crop yields, the system determines maximum yields for each location of a plurality of locations. The system then converts each crop yield value into a relative crop yield by dividing the crop yield value by the maximum crop yield for the location. Using the relative crop yields and the corresponding nitrate values in the soil, the system generates a digital model of relative crop yield as a function of nitrate in the soil during the particular portion of the crop's development.

Abstract: A computerized information processing method for evaluating blood vessels is provided. The method includes acquiring a series of sequences of measurements, each at different time points in at least one cardiac cycle and at a different point along a blood vessel segment of a subject, generating corresponding profiles, calculating a transfer function for a subsegment between two selected points along a blood flow direction, and based thereon determining the physiological property of the subsegment. The measurements can contain information of blood velocity or blood pressure. A processing device and system implementing the information processing method are also provided. This approach can be used to evaluate arteries or veins and can be applied in screening, diagnosis, or prognosis of a variety of vascular diseases. For example, when combined with MRI scan, this approach can be used for non-invasively diagnosing pulmonary hypertension (PH) and chronic obstructive pulmonary disease (COPD), etc.

Abstract: Examples of load balancing across multiple computing nodes of distributed computing systems is described herein. Examples include determining whether an application request is part of a first application request set or a second application request set, and routing the application request to a first computing node or a second computing node of a computing node cluster based on the determination. Other examples include determining whether a database operation request directed to a database is part of a first database operation set or a second database operation set, and routing the database operation request to a first server using a first instance of the database or a second server using a second instance of the database based on the determination. Routing the application and database operation requests based on criteria of the respective request may improve execution efficiency of the requests.

Abstract: A fin-Field Effect Transistor based system on chip (SoC) memory is provided and includes a control block, first logic gates, and row decoder blocks. The control block includes a clock generator circuit that generates an internal clock signal, and a global driver circuit coupled to the clock generator circuit that drives a global clock signal. Each row decoder block includes a second logic gate that receives higher order non-clocked address signals via input terminals, a transmission gate that combines the global clock signal and the higher order non-clocked address signals, third logic gates that receive lower order non-clocked address signals and higher order clocked address signals, and output a combined lower order address and higher order address along with the global clock signal, level shifter circuits that receive the outputs, and word-line driver circuits that generate word-lines based on the output of the level shifter circuits.

Abstract: A computer implemented method for generating digital models of relative crop yield based on nitrate values in the soil is provided. In an embodiment, nitrate measurements from soil during a particular portion of a crop's development and corresponding crop yields are received by an agricultural intelligence computing system. Based, at least in part, on the nitrate measurements and corresponding crop yields, the system determines maximum yields for each location of a plurality of locations. The system then converts each crop yield value into a relative crop yield by dividing the crop yield value by the maximum crop yield for the location. Using the relative crop yields and the corresponding nitrate values in the soil, the system generates a digital model of relative crop yield as a function of nitrate in the soil during the particular portion of the crop's development.

Abstract: A fin-Field Effect Transistor based system on chip (SoC) memory is provided and includes a control block, first logic gates, and row decoder blocks. The control block includes a clock generator circuit that generates an internal clock signal, and a global driver circuit coupled to the clock generator circuit that drives a global clock signal. Each row decoder block includes a second logic gate that receives higher order non-clocked address signals via input terminals, a transmission gate that combines the global clock signal and the higher order non-clocked address signals, third logic gates that receive lower order non-clocked address signals and higher order clocked address signals, and output a combined lower order address and higher order address along with the global clock signal, level shifter circuits that receive the outputs, and word-line driver circuits that generate word-lines based on the output of the level shifter circuits.

Abstract: In an approach for managing network sockets, a computer receives a request to create a network socket to transfer data. The computer identifies information associated with the received request, including one or more of: a default network protocol, one or more supported network protocols, ahead of time initialization, a data transfer policy, a failure policy, and a security policy. The computer creates a second level hash map based on the identified information, wherein the second level hash map includes the supported network socket protocols and a connection state. The computer determines a network protocol to utilize associated with the received request. The computer establishes a connection for the network socket over the determined network protocol.

Abstract: In an approach for managing network sockets, a computer receives a request to create a network socket to transfer data. The computer identifies information associated with the received request, including one or more of: a default network protocol, one or more supported network protocols, ahead of time initialization, a data transfer policy, a failure policy, and a security policy. The computer creates a second level hash map based on the identified information, wherein the second level hash map includes the supported network socket protocols and a connection state. The computer determines a network protocol to utilize associated with the received request. The computer establishes a connection for the network socket over the determined network protocol.

Abstract: A method of camera pose and plane estimation may include detecting a marker within a 3-dimensional (3D) environment by detecting, using a Dynamic Vision Sensor (DVS), a first plurality of light sources arranged in a known shape and blinking at a first frequency, wherein the known shape corresponds to the marker, determining an orientation and an identity of the marker based upon detecting, using the DVS, a second plurality of light sources corresponding to the marker and blinking at a second frequency different from the first frequency. A camera pose for the DVS may be determined based upon the known shape, the orientation, and the identity of the marker using the processor.

Abstract: The present teaching relates to generating a conversational agent. In one example, a plurality of input utterances may be received from a developer. A paraphrase model is obtained. The paraphrase model is generated based on machine translation. For each of the plurality of input utterances, one or more paraphrases of the input utterance are generated based on the paraphrase model. For each of the plurality of input utterances, at least one of the one or more paraphrases is selected based on an instruction from the developer to generate selected paraphrases. The conversational agent is generated based on the plurality of input utterances and the selected paraphrases.

Abstract: Embodiments herein provide a method for reducing power dissipation in a Static Random Access Memory (SRAM) device. The method includes determining, by the tracking circuit, whether at least one SRAM Bit-Cell discharges power from at least one BL exceeding a pre-defined voltage level required for a sense amplifier to perform a read operation. Furthermore, the method includes reducing, by the WL driver, the power discharged from the at least one BL by controlling a WL voltage power supply switch of the WL driver using a SAE signal and adjusting a pulse width of the at least one WL to pull down the at least one WL using a NMOS circuit when the at least one SRAM Bit-Cell discharges the power from the at least one BL exceeding the pre-defined voltage level.

Abstract: Object interaction preservation from design to digital publication is described. In example embodiments, a design includes overlapping objects with object interaction effects. The design has a document object model (DOM). A digital publishing module constructs a DOM tree with each node having an object of the design. The DOM tree is analyzed to identify objects that interact with an overlapped object. Objects with dynamic content and those with no overlapped object can be excluded. A bounding region of each identified object is investigated with regard to object layering data and object interaction attributes. Based on these design aspects, the digital publishing module prepares an object snapshot of the bounding region to reflect an appearance resulting from the interactive objects within the bounding region. The object snapshot is incorporated into a digital publication DOM tree while maintaining the object layering data. Using this DOM tree, the module produces a digital publication.

Abstract: A method for semi-dense depth estimation includes receiving, at an electronic device, a control signal of a speckle pattern projector (SPP and receiving from each sensor of a dynamic vision sensor (DVS) stereo pair, an event stream of pixel intensity change data, wherein the event stream is time-synchronized with the control signal of the SPP. The method further includes performing projected light filtering on the event stream of pixel intensity change data for each sensor of the DVS stereo pair, to generate synthesized event image data, the synthesized event image data having one or more channels, each channel based on an isolated portion of the event stream of pixel intensity change data and performing stereo matching on at least one channel of the synthesized event image data for each sensor of the DVS stereo pair to generate a depth map for at least a portion of the field of view.

Abstract: An apparatus includes a dynamic vision sensor (DVS) configured to output an asynchronous stream of sensor event data, a CMOS image sensor configured to output frames of image data, an inertial measurement unit (IMU), a processor and a memory. The memory contains instructions, which when executed by the processor, cause the apparatus to generate a semantic segmentation of a time-stamped frame, which is based on one or more of an output of the CMOS image sensor, or a synthesized event frame based on an output from the DVS and an output from the IMU over a time interval. The semantic segmentation includes a semantic label associated with a region of the time-stamped frame. When executed, the instructions further cause the apparatus to determine, based on the semantic segmentation, a simplified object representation in a coordinate space, and update a stable semantic map based on the simplified object representation.