Patents by Inventor Ankur N. Shah

Ankur N. Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11494868
    Abstract: An embodiment of a graphics apparatus may include a context engine to determine contextual information, a recommendation engine communicatively coupled to the context engine to determine a recommendation based on the contextual information, and a configuration engine communicatively coupled to the recommendation engine to adjust a configuration of a graphics operation based on the recommendation. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: November 8, 2022
    Assignee: Intel Corporation
    Inventors: Joydeep Ray, Ankur N. Shah, Abhishek R. Appu, Deepak S. Vembar, ElMoustapha Ould-Ahmed-Vall, Atsuo Kuwahara, Travis T. Schluessler, Linda L. Hurd, Josh B. Mastronarde, Vasanth Ranganathan
  • Publication number: 20220334982
    Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.
    Type: Application
    Filed: May 27, 2022
    Publication date: October 20, 2022
    Inventors: NIRANJAN L. COORAY, ABHISHEK R. APPU, ALTUG KOKER, JOYDEEP RAY, BALAJI VEMBU, PATTABHIRAMAN K, DAVID PUFFER, DAVID J. COWPERTHWAITE, RAJESH M. SANKARAN, SATYESHWAR SINGH, SAMEER KP, ANKUR N. SHAH, KUN TIAN
  • Patent number: 11461959
    Abstract: The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles in one or more exclusion zones.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: October 4, 2022
    Assignee: Intel Corporation
    Inventors: Prasoonkumar Surti, Karthik Vaidyanathan, Atsuo Kuwahara, Hugues Labbe, Sameer Kp, Jonathan Kennedy, Abhishek R. Appu, Jeffery S. Boles, Balaji Vembu, Michael Apodaca, Slawomir Grajewski, Gabor Liktor, David M. Cimini, Andrew T. Lauritzen, Travis T. Schluessler, Murali Ramadoss, Abhishek Venkatesh, Joydeep Ray, Kai Xiao, Ankur N. Shah, Altug Koker
  • Patent number: 11436696
    Abstract: An apparatus and method for provisioning virtualized tile-based graphics processing circuitry. For example, one embodiment of an apparatus comprises: processing resources to process commands including graphics commands and generate results; resource partitioning circuitry to partition the processing resources into a plurality of tiles in accordance with a specified tile-based resource allocation policy; and graphics virtualization circuitry to perform tile-based allocation of the processing resources to a plurality of virtual machines in accordance with a specified virtualization policy, the virtual machines to be executed in a virtualized execution environment.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: September 6, 2022
    Assignee: Intel Corporation
    Inventors: Ankur N. Shah, Nishanth Reddy Pendluru, Joseph Koston, Murali Ramadoss
  • Publication number: 20220270317
    Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The graphics subsystem may include a first graphics engine to process a graphics workload, and a second graphics engine to offload at least a portion of the graphics workload from the first graphics engine. The second graphics engine may include a low precision compute engine. The system may further include a wearable display housing the second graphics engine. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: December 29, 2021
    Publication date: August 25, 2022
    Inventors: Atsuo Kuwahara, Deepak S. Vembar, Chandrasekaran Sakthivel, Radhakrishnan Venkataraman, Brent E. Insko, Anupreet S. Kalra, Hugues Labbe, Abhishek R. Appu, Ankur N. Shah, Joydeep Ray, Elmoustapha Ould-Ahmed-Vall, Prasoonkumar Surti, Murali Ramadoss
  • Patent number: 11392502
    Abstract: An embodiment of an electronic processing system may include an application processor, system memory communicatively coupled to the application processor, a graphics processor communicatively coupled to the application processor, graphics memory communicatively coupled to the graphics processor, and persistent storage media communicatively coupled to the application processor and the graphics processor to store one or more graphics assets, wherein the graphics processor is to access the one or more graphics asset mapped from the persistent storage media. The persistent storage media may include a low latency, high capacity, and byte-addressable nonvolatile memory. The one or more graphics assets may include one or more of a mega-texture and terrain data. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: July 19, 2022
    Assignee: Intel Corporation
    Inventors: Jianfang Zhu, Cristiano J. Ferreira, Bo Qiu, Ajit Krisshna Nandyal Lakshman, Nikhil Talpallikar, Deepak Gandiga Shivakumar, Brandt M. Guttridge, Kim Pallister, Frank J. Soqui, Anand Srivatsa, Travis T. Schluessler, Abhishek R. Appu, Ankur N. Shah, Joydeep Ray, Altug Koker, Jonathan Kennedy
  • Publication number: 20220187897
    Abstract: Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width reduction based on throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamically configurable bus widths and frequencies.
    Type: Application
    Filed: December 27, 2021
    Publication date: June 16, 2022
    Applicant: Intel Corporation
    Inventors: Mohammed Tameem, Altug Koker, Kiran C. Veernapu, Abhishek R. Appu, Ankur N. Shah, Joydeep Ray, Travis T. Schluessler, Jonathan Kennedy
  • Patent number: 11360914
    Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: June 14, 2022
    Assignee: Intel Corporation
    Inventors: Niranjan L. Cooray, Abhishek R. Appu, Altug Koker, Joydeep Ray, Balaji Vembu, Pattabhiraman K, David Puffer, David J. Cowperthwaite, Rajesh M. Sankaran, Satyeshwar Singh, Sameer Kp, Ankur N. Shah, Kun Tian
  • Publication number: 20220137967
    Abstract: Embodiments are generally directed to graphics processor data access and sharing. An embodiment of an apparatus includes a circuit element to produce a result in processing of an application; a load-store unit to receive the result and generate pre-fetch information for a cache utilizing the result; and a prefetch generator to produce prefetch addresses based at least in part on the pre-fetch information; wherein the load-store unit is to receive software assistance for prefetching, and wherein generation of the pre-fetch information is based at least in part on the software assistance.
    Type: Application
    Filed: March 14, 2020
    Publication date: May 5, 2022
    Applicant: Intel Corporation
    Inventors: Altug Koker, Varghese George, Aravindh Anantaraman, Valentin Andrel, Abhishek R. Appu, Niranjan Cooray, Nicolas Galoppo Von Borries, Mike MacPherson, Subramaniam Maiyuran, ElMoustapha Ould-Ahmed-Vall, David Puffer, Vasanth Ranganathan, Joydeep Ray, Ankur N. Shah, Lakshminarayanan Striramassarma, Prasoonkumar Surti, Saurabh Tangri
  • Publication number: 20220121421
    Abstract: Methods and apparatus relating to techniques for multi-tile memory management. In an example, an apparatus comprises a cache memory, a high-bandwidth memory, a shader core communicatively coupled to the cache memory and comprising a processing element to decompress a first data element extracted from an in-memory database in the cache memory and having a first bit length to generate a second data element having a second bit length, greater than the first bit length, and an arithmetic logic unit (ALU) to compare the data element to a target value provided in a query of the in-memory database. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: March 14, 2020
    Publication date: April 21, 2022
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Altug Koker, Aravindh Anantaraman, Elmoustapha Ould-Ahmed-Vall, Valentin Andrei, Nicolas Galoppo Von Borries, Varghese George, Mike Macpherson, Subramaniam Maiyuran, Joydeep Ray, Lakshminarayana Striramassarma, Scott Janus, Brent Insko, Vasanth Ranganathan, Kamal Sinha, Arthur Hunter, Prasoonkumar Surti, David Puffer, James Valerio, Ankur N. Shah
  • Publication number: 20220113783
    Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: August 25, 2021
    Publication date: April 14, 2022
    Applicant: INTEL CORPORATION
    Inventors: Altug Koker, Abhishek R. Appu, Kiran C. Veernapu, Joydeep Ray, Balaji Vembu, Prasoonkumar Surti, Kamal Sinha, Eric J. Hoekstra, Wenyin Fu, Nikos Kaburlasos, Bhushan M. Borole, Travis T. Schluessler, Ankur N. Shah, Jonathan Kennedy
  • Patent number: 11302413
    Abstract: Systems, apparatuses and methods provide technology that identifies a redundant portion of a packaged on-die memory and detects, during a field test of the packaged on-die memory, one or more failed cells in the packaged on-die memory. Additionally, one or more memory cells in the redundant portion are substituted for the one or more failed memory cells.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: April 12, 2022
    Assignee: Intel Corporation
    Inventors: Altug Koker, Travis T. Schluessler, Ankur N. Shah, Abhishek R. Appu, Joydeep Ray, Jonathan Kennedy
  • Publication number: 20220076480
    Abstract: Systems, apparatuses, and methods may provide for technology to process graphics data in a virtual gaming environment. The technology may identify, from graphics data in a graphics application, redundant graphics calculations relating to common frame characteristics of one or more graphical scenes to be shared between client game devices of a plurality of users and calculate, in response to the identified redundant graphics calculations, frame characteristics relating to the one or more graphical scenes. Additionally, the technology may send, over a computer network, the calculation of the frame characteristics to the client game devices.
    Type: Application
    Filed: September 17, 2021
    Publication date: March 10, 2022
    Inventors: Jonathan Kennedy, Gabor Liktor, Jeffery S. Boles, Slawomir Grajewski, Balaji Vembu, Travis T. Schluessler, Abhishek R. Appu, Ankur N. Shah, Joydeep Ray, Altug Koker, Jacek Kwiatkowski
  • Patent number: 11257180
    Abstract: Systems, apparatuses, and methods may provide for technology to process graphical data, and to modify a runtime environment in a parallel computing platform for a graphic environment.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: February 22, 2022
    Assignee: Intel Corporation
    Inventors: Travis T. Schluessler, Abhishek R. Appu, Ankur N. Shah, Joydeep Ray, Altug Koker, Jacek Kwiatkowski, Ingo Wald, Jefferson Amstutz, Johannes Guenther, Gabor Liktor, Elmoustapha Ould-Ahmed-Vall
  • Publication number: 20220050520
    Abstract: An embodiment of a graphics apparatus may include a facial expression detector to detect a facial expression of a user, and a parameter adjuster communicatively coupled to the facial expression detector to adjust a graphics parameter based on the detected facial expression of the user. The detected facial expression may include one or more of a squinting, blinking, winking, and facial muscle tension of the user. The graphics parameter may include one or more of a frame resolution, a screen contrast, a screen brightness, and a shading rate. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: August 30, 2021
    Publication date: February 17, 2022
    Applicant: Intel Corporation
    Inventors: Travis T. Schluessler, Joydeep Ray, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Jefferson Amstutz, Carson Brownlee, Vivek Tiwari, Sayan Lahiri, Kai Xiao, Abhishek R. Appu, ElMoustapha Ould-Ahmed-Vall, Deepak S. Vembar, Ankur N. Shah, Balaji Vembu, Josh B. Mastronarde
  • Publication number: 20220012843
    Abstract: An embodiment of a graphics apparatus may include a mask buffer to store a mask, a shader communicatively coupled to the mask buffer to apply the mask to a first shader pass, and a resolver communicatively coupled to the mask buffer to apply the mask to a resolve pass. The resolver may be configured to exclude a sample location not covered by the mask in the resolve pass. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: September 24, 2021
    Publication date: January 13, 2022
    Applicant: Intel Corporation
    Inventors: Hugues Labbe, Tomer Bar-On, Kai Xiao, Ankur N. Shah, John G. Gierach
  • Patent number: 11216915
    Abstract: Systems, apparatuses and methods may provide for technology that identifies, at an image post-processor, unresolved surface data and identifies, at the image post-processor, control data associated with the unresolved surface data. Additionally, the technology may resolve, at the image post-processor, the unresolved surface data and the control data into a final image.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: January 4, 2022
    Assignee: Intel Corporation
    Inventors: Tomer Bar-On, Hugues Labbe, Adam T. Lake, Kai Xiao, Ankur N. Shah, Johannes Guenther, Abhishek R. Appu, Joydeep Ray, Deepak S. Vembar, ElMoustapha Ould-Ahmed-Vall
  • Patent number: 11217004
    Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The graphics subsystem may include a first graphics engine to process a graphics workload, and a second graphics engine to offload at least a portion of the graphics workload from the first graphics engine. The second graphics engine may include a low precision compute engine. The system may further include a wearable display housing the second graphics engine. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 4, 2022
    Assignee: Intel Corporation
    Inventors: Atsuo Kuwahara, Deepak S. Vembar, Chandrasekaran Sakthivel, Radhakrishnan Venkataraman, Brent E. Insko, Anupreet S. Kalra, Hugues Labbe, Abhishek R. Appu, Ankur N. Shah, Joydeep Ray, Elmoustapha Ould-Ahmed-Vall, Prasoonkumar Surti, Murali Ramadoss
  • Patent number: 11209892
    Abstract: Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width reduction based on the instantaneous throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamic bus module to configure a bus width for a client of the interconnect fabric based on throughput demand from the client.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: December 28, 2021
    Assignee: Intel Corporation
    Inventors: Mohammed Tameem, Altug Koker, Kiran C. Veernapu, Abhishek R. Appu, Ankur N. Shah, Joydeep Ray, Travis T. Schluessler, Jonathan Kennedy
  • Publication number: 20210398243
    Abstract: An apparatus and method for provisioning virtualized tile-based graphics processing circuitry. For example, one embodiment of an apparatus comprises: processing resources to process commands including graphics commands and generate results; resource partitioning circuitry to partition the processing resources into a plurality of tiles in accordance with a specified tile-based resource allocation policy; and graphics virtualization circuitry to perform tile-based allocation of the processing resources to a plurality of virtual machines in accordance with a specified virtualization policy, the virtual machines to be executed in a virtualized execution environment.
    Type: Application
    Filed: June 29, 2021
    Publication date: December 23, 2021
    Applicant: Intel Corporation
    Inventors: Ankur N. Shah, Nishanth Reddy Pendluru, Joseph Koston, Murali Ramadoss