Patents by Inventor Anthony Babella

Anthony Babella has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7904701
    Abstract: Provided are a method and system for activating a design test mode in a graphics card having multiple execution units. A design test mode is activated in a graphics module comprising multiple execution units coupled to a cache on a bus. The bus is configured to return test instructions from the cache to the execution units in response to a request from one execution unit for the test instructions from the cache in the design test mode. The execution units execute the test instructions during the design test mode. Interrupts are prevented during the design test mode.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: March 8, 2011
    Assignee: Intel Corporation
    Inventors: Anthony Babella, Allan Wong, Lance Cheney, Brian D. Rauchfuss
  • Patent number: 7802146
    Abstract: Provided are a method and system for loading test data into execution units in a graphics card to test the execution units. Test instructions are loaded into a cache in a graphics module comprising multiple execution units coupled to the cache on a bus during a design test mode. The cache instructions are concurrently transferred to an instruction queue of each execution unit to concurrently load the cache instructions into the instruction queues of the execution units. The execution units concurrently execute the cache instructions to fetch test instructions from the cache to load into memories of the execution units and execute during the design test mode.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: September 21, 2010
    Assignee: Intel Corporation
    Inventors: Allan Wong, Ke Yin, Naveen Matam, Anthony Babella, Wing Hang Wong
  • Publication number: 20080307202
    Abstract: Provided are a method and system for loading test data into execution units in a graphics card to test the execution units. Test instructions are loaded into a cache in a graphics module comprising multiple execution units coupled to the cache on a bus during a design test mode. The cache instructions are concurrently transferred to an instruction queue of each execution unit to concurrently load the cache instructions into the instruction queues of the execution units. The execution units concurrently execute the cache instructions to fetch test instructions from the cache to load into memories of the execution units and execute during the design test mode.
    Type: Application
    Filed: June 7, 2007
    Publication date: December 11, 2008
    Inventors: Allan WONG, Ke YIN, Naveen MATAM, Anthony BABELLA, Wing Hang WONG
  • Publication number: 20080307261
    Abstract: Provided are a method and system for activating a design test mode in a graphics card having multiple execution units. A design test mode is activated in a graphics module comprising multiple execution units coupled to a cache on a bus. The bus is configured to return test instructions from the cache to the execution units in response to a request from one execution unit for the test instructions from the cache in the design test mode. The execution units execute the test instructions during the design test mode. Interrupts are prevented during the design test mode.
    Type: Application
    Filed: June 7, 2007
    Publication date: December 11, 2008
    Inventors: Anthony BABELLA, Allan WONG, Lance CHENEY, Brian D. RAUCHFUSS
  • Patent number: 6738939
    Abstract: An apparatus with a generator to generate a pattern and multiple scan chains configured to receive the pattern from the generator. Multiple signature registers coupled to the scan chains, to receive an output of at least one of scan chains during a mode of the integrated device.
    Type: Grant
    Filed: May 21, 2001
    Date of Patent: May 18, 2004
    Assignee: Intel Corporation
    Inventors: Kapila B. Udawatta, Anthony Babella
  • Patent number: 6668347
    Abstract: An integrated circuit having a central built-in self-test unit (BIST) that uses internal scan chains for testing embedded memory modules. The embedded memory modules receive address and data signals from a set of input flip-flops configured to form a scan chain. The BIST is coupled to an input scan chain and includes a pattern generator to shift a test pattern into the input scan chain for testing the embedded memory modules. Output flip-flops capture data from the embedded memory modules are also configured as a scan chain. The BIST includes address control logic to bypass the normal addressing logic of the embedded memory module when the BIST operates is operating in a memory test mode.
    Type: Grant
    Filed: May 8, 2000
    Date of Patent: December 23, 2003
    Assignee: Intel Corporation
    Inventors: Anthony Babella, Patrick P. Chan, Chih-Jen (Mike) Lin, Thomas J. Shewchuk, Daniel S. Lee
  • Patent number: 6650136
    Abstract: A circuit to analyze or test a first or second logic coupled to an input/output circuit by storing a plurality of signals into a plurality of flip flops. The flip flops store the plurality of signals for a first mode of operation to observe at least one node within the first logic. Also, the flip flops load data values in response to control logic for a second mode of operation to control at least one node within the second logic.
    Type: Grant
    Filed: February 16, 2001
    Date of Patent: November 18, 2003
    Assignee: Intel Corporation
    Inventors: Anthony Babella, Kapila B. Udawatta, Razi Uddin
  • Publication number: 20020174393
    Abstract: An apparatus with a generator to generate a pattern and multiple scan chains configured to receive the pattern from the generator. Multiple signature registers coupled to the scan chains, to receive an output of at least one of scan chains during a mode of the integrated device.
    Type: Application
    Filed: May 21, 2001
    Publication date: November 21, 2002
    Inventors: Kapila B. Udawatta, Anthony Babella
  • Publication number: 20020113614
    Abstract: A circuit to analyze or test a first or second logic coupled to an input/output circuit by storing a plurality of signals into a plurality of flip flops. The flip flops store the plurality of signals for a first mode of operation to observe at least one node within the first logic. Also, the flip flops load data values in response to control logic for a second mode of operation to control at least one node within the second logic.
    Type: Application
    Filed: February 16, 2001
    Publication date: August 22, 2002
    Inventors: Anthony Babella, Kapila B. Udawatta, Razi Uddin