Patents by Inventor Anthony Domenicucci
Anthony Domenicucci has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080116483Abstract: A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom.Type: ApplicationFiled: February 7, 2008Publication date: May 22, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen Bedell, Huajie Chen, Anthony Domenicucci, Keith Fogel, Richard Murphy, Devendra Sadana
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Publication number: 20070128867Abstract: The present invention provides a method for enhancing uni-directional diffusion of a metal during silicidation by using a metal-containing silicon alloy in conjunction with a first anneal in which two distinct thermal cycles are performed. The first thermal cycle of the first anneal is performed at a temperature that is capable of enhancing the uni-directional diffusion of metal, e.g., Co and/or Ni, into a Si-containing layer. The first thermal cycle causes an amorphous metal-containing silicide to form. The second thermal cycle is performed at a temperature that converts the amorphous metal-containing silicide into a crystallized metal rich silicide that is substantially non-etchable as compared to the metal-containing silicon alloy layer or a pure metal-containing layer. Following the first anneal, a selective etch is performed to remove any unreacted metal-containing alloy layer from the structure.Type: ApplicationFiled: February 7, 2007Publication date: June 7, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony Domenicucci, Bradley Jones, Christian Lavoie, Robert Purtell, Yun Wang, Kwong Wong
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Publication number: 20070105350Abstract: A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a sufficient temperature, the nature of the dislocation motion is such that the strain-relieving defects move downward into the thin Si layer when the buried oxide behaves semi-viscously. The thin Si layer is consumed by oxidation of the buried oxide/thin Si interface. This can be accomplished by using internal oxidation at high temperatures. In this way the role of the original thin Si layer is to act as a sacrificial defect sink during relaxation of the SiGe alloy that can later be consumed using internal oxidation.Type: ApplicationFiled: January 2, 2007Publication date: May 10, 2007Applicant: International Business Machines CorporationInventors: Stephen Bedell, Huajie Chen, Anthony Domenicucci, Keith Fogel, Devendra Sadana
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Publication number: 20060097167Abstract: A method for enhancing spatial resolution of a transmission electron microscopy TEM) system configured for electron holography. In an exemplary embodiment, the method includes configuring a first lens to form an initial virtual source with respect to an incident parallel beam, the initial virtual source positioned at a back focal plane of said first lens. A second lens is configured to form an intermediate virtual source with respect to the incident parallel beam, the position of said intermediate virtual source being dependent upon a focal length of the first lens and a focal length of the second lens. A third lens is configured to form a final virtual source with respect to the incident parallel beam, wherein the third lens has a focal length such that a front focal plane of the third lens lies beyond the position of the intermediate virtual source, with respect to a biprism location.Type: ApplicationFiled: October 25, 2004Publication date: May 11, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony Domenicucci, Yun-Yu Wang
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Publication number: 20060081837Abstract: A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 ?) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.Type: ApplicationFiled: December 2, 2005Publication date: April 20, 2006Applicant: International Business Machines CorporationInventors: Stephen Bedell, Anthony Domenicucci, Keith Fogel, Effendi Leobandung, Devendra Sadana
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Publication number: 20060065830Abstract: A method for preparing a transmission electron microscopy (TEM) sample for electron holography includes forming a sacrificial material over an area of interest on the sample, and polishing the sample to a desired thickness, wherein the area of interest is protected from rounding during the polishing. The sacrificial material is removed from the sample following the polishing.Type: ApplicationFiled: September 30, 2004Publication date: March 30, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas Bauer, Steven Boettcher, Anthony Domenicucci, John Gaudiello, Leon Kimball, Jeffrey McMurray, Yun-Yu Wang
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Publication number: 20060057844Abstract: The present invention provides a method for enhancing uni-directional diffusion of a metal during silicidation by using a metal-containing silicon alloy in conjunction with a first anneal in which two distinct thermal cycles are performed. The first thermal cycle of the first anneal is performed at a temperature that is capable of enhancing the uni-directional diffusion of metal, e.g., Co and/or Ni, into a Si-containing layer. The first thermal cycle causes an amorphous metal-containing silicide to form. The second thermal cycle is performed at a temperature that converts the amorphous metal-containing silicide into a crystallized metal rich silicide that is substantially non-etchable as compared to the metal-containing silicon alloy layer or a pure metal-containing layer. Following the first anneal, a selective etch is performed to remove any unreacted metal-containing alloy layer from the structure.Type: ApplicationFiled: September 14, 2004Publication date: March 16, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony Domenicucci, Bradley Jones, Christian Lavoie, Robert Purtell, Yun Yu Wang, Kwong Hon Wong
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Publication number: 20060030133Abstract: Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.Type: ApplicationFiled: August 19, 2005Publication date: February 9, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul Agnello, Stephen Bedell, Robert Dennard, Anthony Domenicucci, Keith Fogel, Devendra Sadana
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Publication number: 20060001089Abstract: A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 ?) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.Type: ApplicationFiled: July 2, 2004Publication date: January 5, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen Bedell, Anthony Domenicucci, Keith Fogel, Effendi Leobandung, Devendra Sadana
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Publication number: 20050208780Abstract: A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom.Type: ApplicationFiled: January 5, 2005Publication date: September 22, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen Bedell, Anthony Domenicucci, Keith Fogel, Devendra Sadana
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Publication number: 20050145941Abstract: A strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET.Type: ApplicationFiled: January 7, 2004Publication date: July 7, 2005Applicant: International Business Machines CorporationInventors: Stephen Bedell, Kevin Chan, Dureseti Chidambarrao, Silke Christiansen, Jack Chu, Anthony Domenicucci, Kam-Leung Lee, Anda Mocuta, John Ott, Qiqing Ouyang
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Publication number: 20050045819Abstract: A method and calibration standard for fabricating on a single substrate a series of crystalline pairs such that the d-spacing difference between the pairs will generate Moire fringes of the correct spacings to optimally calibrate the magnification settings of an electron microscope over a variety of magnification settings in the range of 5000× to 200,000×. The invention enables the tailoring of Moire fringe spacings to a desired magnification setting for calibration purposes by fabricating a series of patterns on a single substrate whereby each magnification setting is easily calibrated using a specific SGOI structure that is selected by a simple x-y translation across the top plan surface of the SGOI structure, therein eliminating the need for removing calibration samples in and out of the electron microscope. The method and calibration standard may be used for calibrating electron microscopes, such as, scanning transmission electron microscopes and transmission electron microscopes.Type: ApplicationFiled: August 29, 2003Publication date: March 3, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen Bedell, John Bruley, Anthony Domenicucci, Devendra Sadana
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Publication number: 20050003229Abstract: A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a sufficient temperature, the nature of the dislocation motion is such that the strain-relieving defects move downward into the thin Si layer when the buried oxide behaves semi-viscously. The thin Si layer is consumed by oxidation of the buried oxide/thin Si interface. This can be accomplished by using internal oxidation at high temperatures. In this way the role of the original thin Si layer is to act as a sacrificial defect sink during relaxation of the SiGe alloy that can later be consumed using internal oxidation.Type: ApplicationFiled: July 1, 2003Publication date: January 6, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen Bedell, Huajie Chen, Anthony Domenicucci, Keith Fogel, Devendra Sadana
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Patent number: 6475893Abstract: A method for preparing a semiconductor material for formation of a silicide layer on selected areas thereupon is disclosed. In an exemplary embodiment of the invention, the method includes removing at least one of a nitride and an oxynitride film from the selected areas, removing metallic particles from the selected areas, removing surface particles from the selected areas, removing organics from the selected areas, and removing an oxide layer from the selected areas.Type: GrantFiled: March 30, 2001Date of Patent: November 5, 2002Assignee: International Business Machines CorporationInventors: Kenneth J. Giewont, Yun Yu Wang, Russell Arndt, Craig Ransom, Judith Coffin, Anthony Domenicucci, Michael MacDonald, Brian E. Johnson
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Publication number: 20020142616Abstract: A method for preparing a semiconductor material for the formation of a silicide layer on selected areas thereupon is disclosed. In an exemplary embodiment of the invention, the method includes removing at least one of a nitride and an oxynitride film from the selected areas, removing metallic particles from the selected areas, removing surface particles from the selected areas, removing organics from the selected areas, and removing an oxide layer from the selected areas.Type: ApplicationFiled: March 30, 2001Publication date: October 3, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kenneth J. Giewont, Yun Yu Wang, Russell Arndt, Craig Ransom, Judith Coffin, Anthony Domenicucci, Michael MacDonald, Brian E. Johnson