Patents by Inventor Anthony G. Aipperspach
Anthony G. Aipperspach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11018084Abstract: An integrated circuit (IC) can be configured to provide a managed power distribution to circuits within a plurality of regions of the IC. Each region of the plurality of regions can include a corresponding set of circuits that are electrically connected to a corresponding virtual power island (VPI) within said each region. A global power distribution structure within the IC can be configured to be electrically interconnected to an off-chip voltage supply. The IC can also include a plurality of sets of vertical interconnects (VIs), each set of VIs electrically interconnected to a VPI within a corresponding region. Each set of VIs can also be connected to the global power distribution structure, and can be used to provide a specifically managed voltage through a VPI to a set of circuits within a corresponding region of the IC.Type: GrantFiled: July 26, 2019Date of Patent: May 25, 2021Assignee: International Business Machines CorporationInventors: Anthony G. Aipperspach, Jeffrey D. Brown, Kirk D. Peterson, John E. Sheets, II
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Patent number: 10580730Abstract: An integrated circuit (IC) can be configured to provide a managed power distribution to circuits within a plurality of regions of the IC. Each region of the plurality of regions can include a corresponding set of circuits that are electrically connected to a corresponding virtual power island (VPI) within said each region. A global power distribution structure within the IC can be configured to be electrically interconnected to an off-chip voltage supply. The IC can also include a plurality of sets of vertical interconnects (VIs), each set of VIs electrically interconnected to a VPI within a corresponding region. Each set of VIs can also be connected to the global power distribution structure, and can be used to provide a specifically managed voltage through a VPI to a set of circuits within a corresponding region of the IC.Type: GrantFiled: November 16, 2017Date of Patent: March 3, 2020Assignee: International Business Machines CorporationInventors: Anthony G. Aipperspach, Jeffrey D. Brown, Kirk D. Peterson, John E. Sheets, II
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Publication number: 20190348361Abstract: An integrated circuit (IC) can be configured to provide a managed power distribution to circuits within a plurality of regions of the IC. Each region of the plurality of regions can include a corresponding set of circuits that are electrically connected to a corresponding virtual power island (VPI) within said each region. A global power distribution structure within the IC can be configured to be electrically interconnected to an off-chip voltage supply. The IC can also include a plurality of sets of vertical interconnects (VIs), each set of VIs electrically interconnected to a VPI within a corresponding region. Each set of VIs can also be connected to the global power distribution structure, and can be used to provide a specifically managed voltage through a VPI to a set of circuits within a corresponding region of the IC.Type: ApplicationFiled: July 26, 2019Publication date: November 14, 2019Inventors: Anthony G. Aipperspach, Jeffrey D. Brown, Kirk D. Peterson, John E. Sheets, II
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Patent number: 10311966Abstract: A system and integrated circuits are provided for determining performance metrics over a plurality of cycles of an input signal using on-chip diagnostic circuitry. The system comprises a trigger generation module configured to generate a trigger signal, and diagnostic circuitry coupled with the trigger generation module. The diagnostic circuitry comprises a memory comprising a plurality of data lines, and a plurality of delay elements, each delay element of the plurality of delay elements connected between consecutive data lines of the plurality of data lines. The diagnostic circuitry is configured to receive at least one input signal, and write, upon receiving the trigger signal, values on the plurality of data lines to the memory, thereby acquiring samples of a plurality of cycles of the input signal.Type: GrantFiled: February 22, 2016Date of Patent: June 4, 2019Assignee: International Business Machines CorporationInventors: Anthony G. Aipperspach, Derick G. Behrends, Todd A. Christensen, Jeffrey M. Scherer
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Publication number: 20190148284Abstract: An integrated circuit (IC) can be configured to provide managed power distribution to circuits within a plurality of regions of the IC. Each region of the plurality of regions can include a corresponding set of circuits that are electrically connected to a corresponding virtual power island (VPI) within the region. A global power distribution structure within the IC can be configured to be electrically interconnected to an off-chip voltage supply. The IC can also include a plurality of sets of vertical interconnects (VIs), each set of VIs electrically interconnected to a VPI within a corresponding region. Each set of VIs can also be connected to the global power distribution structure, and can be used to provide a specified, managed voltage, through a VPI, to a set of circuits within a corresponding region of the IC.Type: ApplicationFiled: November 16, 2017Publication date: May 16, 2019Inventors: Anthony G. Aipperspach, Jeffrey D. Brown, Kirk D. Peterson, John E. Sheets, II
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Publication number: 20170242066Abstract: A system and integrated circuits are disclosed for determining performance metrics over a plurality of cycles of an input signal using on-chip diagnostic circuitry. The system comprises a trigger generation module configured to generate a trigger signal, and diagnostic circuitry coupled with the trigger generation module. The diagnostic circuitry comprises a memory comprising a plurality of data lines, and a plurality of delay elements, each delay element of the plurality of delay elements connected between consecutive data lines of the plurality of data lines. The diagnostic circuitry is configured to receive at least one input signal, and write, upon receiving the trigger signal, values on the plurality of data lines to the memory, thereby acquiring samples of a plurality of cycles of the input signal.Type: ApplicationFiled: February 22, 2016Publication date: August 24, 2017Inventors: Anthony G. AIPPERSPACH, Derick G. BEHRENDS, Todd A. CHRISTENSEN, Jeffrey M. SCHERER
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Patent number: 9715905Abstract: A computing system, processing unit, and method are disclosed for detecting a maximum voltage power supply for performing memory testing. The method includes generating, using a sense amplifier of a processing unit and based on a timing of a received pulse signal, first and second drive signals that collectively indicate which of first and second voltages is greater, the first and second voltages produced by respective first and second power supplies. The method also includes coupling, based on the first and second drive signals, the power supply corresponding to the relatively greater voltage of the first and second voltages with the memory.Type: GrantFiled: August 12, 2015Date of Patent: July 25, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony G. Aipperspach, Derick G. Behrends, Todd A. Christensen, Jeffrey M. Scherer
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Patent number: 9712170Abstract: A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input signal. The level-shifting latch circuit also includes a first latch, having a first node and a second node, for storing the input signal in the first voltage domain, and a second latch, having a third node and a fourth node, for storing the input signal in the second voltage domain. In addition, the level-shifting circuit also includes a first switching element which provides a path to transfer a low voltage at the first node to the third node, and a second switching element which provides a path to transfer a low voltage at the second node to the fourth node.Type: GrantFiled: December 24, 2014Date of Patent: July 18, 2017Assignee: International Bueinss Machines CorporationInventors: Anthony G. Aipperspach, Steven J. Baumgartner, Charles P. Geer, David P. Paulsen, David W. Siljenberg, Alan P. Wagstaff
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Patent number: 9583938Abstract: An electrostatic discharge (ESD) protection device to manage leakage current can, in response to a power good (PGOOD) signal, draw the gate terminal of an ESD clamp device to a voltage below ground. The device also drives an inverted copy of the PGOOD signal to a gated inverter, which can inhibit the gated inverter output from drawing the ESD clamp device gate terminal to ground. The ESD protection device also includes the ESD clamp device to, in response to the gate terminal of the ESD clamp device being drawn to a bias voltage less than ground, allow a leakage current to flow through the ESD clamp device that is less than a leakage current allowed to flow in response to the ESD clamp device gate terminal being drawn to ground.Type: GrantFiled: May 1, 2015Date of Patent: February 28, 2017Assignee: International Business Machines CorporationInventors: Anthony G. Aipperspach, Derick G. Behrends, Todd A. Christensen, David W. Siljenberg
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Publication number: 20170047099Abstract: A computing system, processing unit, and method are disclosed for detecting a maximum voltage power supply for performing memory testing. The method includes generating, using a sense amplifier of a processing unit and based on a timing of a received pulse signal, first and second drive signals that collectively indicate which of first and second voltages is greater, the first and second voltages produced by respective first and second power supplies. The method also includes coupling, based on the first and second drive signals, the power supply corresponding to the relatively greater voltage of the first and second voltages with the memory.Type: ApplicationFiled: August 12, 2015Publication date: February 16, 2017Inventors: Anthony G. AIPPERSPACH, Derick G. BEHRENDS, Todd A. CHRISTENSEN, Jeffrey M. SCHERER
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Patent number: 9553584Abstract: A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input signal. The level-shifting latch circuit also includes a first latch, having a first node and a second node, for storing the input signal in the first voltage domain, and a second latch, having a third node and a fourth node, for storing the input signal in the second voltage domain. In addition, the level-shifting circuit also includes a first switching element which provides a path to transfer a low voltage at the first node to the third node, and a second switching element which provides a path to transfer a low voltage at the second node to the fourth node.Type: GrantFiled: December 23, 2014Date of Patent: January 24, 2017Assignee: International Business Machines CorporationInventors: Anthony G. Aipperspach, Steven J. Baumgartner, Charles P. Geer, David P. Paulsen, David W. Siljenberg, Alan P. Wagstaff
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Patent number: 9496712Abstract: An electrostatic discharge (ESD) protection device to manage leakage current can, in response to a power good (PGOOD) signal, draw the gate terminal of an ESD clamp device to a voltage below ground. The device also drives an inverted copy of the PGOOD signal to a gated inverter, which can inhibit the gated inverter output from drawing the ESD clamp device gate terminal to ground. The ESD protection device also includes the ESD clamp device to, in response to the gate terminal of the ESD clamp device being drawn to a bias voltage less than ground, allow a leakage current to flow through the ESD clamp device that is less than a leakage current allowed to flow in response to the ESD clamp device gate terminal being drawn to ground.Type: GrantFiled: April 1, 2016Date of Patent: November 15, 2016Assignee: International Business Machines CorporationInventors: Anthony G. Aipperspach, Derick G. Behrends, Todd A. Christensen, David W. Siljenberg
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Publication number: 20160322813Abstract: An electrostatic discharge (ESD) protection device to manage leakage current can, in response to a power good (PGOOD) signal, draw the gate terminal of an ESD clamp device to a voltage below ground. The device also drives an inverted copy of the PGOOD signal to a gated inverter, which can inhibit the gated inverter output from drawing the ESD clamp device gate terminal to ground. The ESD protection device also includes the ESD clamp device to, in response to the gate terminal of the ESD clamp device being drawn to a bias voltage less than ground, allow a leakage current to flow through the ESD clamp device that is less than a leakage current allowed to flow in response to the ESD clamp device gate terminal being drawn to ground.Type: ApplicationFiled: April 1, 2016Publication date: November 3, 2016Inventors: Anthony G. Aipperspach, Derick G. Behrends, Todd A. Christensen, David W. Siljenberg
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Publication number: 20160322812Abstract: An electrostatic discharge (ESD) protection device to manage leakage current can, in response to a power good (PGOOD) signal, draw the gate terminal of an ESD clamp device to a voltage below ground. The device also drives an inverted copy of the PGOOD signal to a gated inverter, which can inhibit the gated inverter output from drawing the ESD clamp device gate terminal to ground. The ESD protection device also includes the ESD clamp device to, in response to the gate terminal of the ESD clamp device being drawn to a bias voltage less than ground, allow a leakage current to flow through the ESD clamp device that is less than a leakage current allowed to flow in response to the ESD clamp device gate terminal being drawn to ground.Type: ApplicationFiled: May 1, 2015Publication date: November 3, 2016Inventors: Anthony G. Aipperspach, Derick G. Behrends, Todd A. Christensen, David W. Siljenberg
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Patent number: 9424389Abstract: A method and circuit for implementing enhanced performance dynamic evaluation, and a design structure on which the subject circuit resides are provided. The dynamic evaluation circuit includes a combined precharge and keeper device connected to a precharge node. The dynamic evaluation circuit includes control logic providing a control input to the combined precharge and keeper device. The combined precharge and keeper device responsive to the control input holds the precharge node precharged when the precharge node is not discharged early in an evaluate cycle.Type: GrantFiled: December 18, 2014Date of Patent: August 23, 2016Assignee: International Business Machines CorporationInventors: Anthony G. Aipperspach, Derick G. Behrends, Todd A. Christensen, Jesse D. Smith
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Patent number: 9396303Abstract: A method and circuit for implementing enhanced performance dynamic evaluation, and a design structure on which the subject circuit resides are provided. The dynamic evaluation circuit includes a combined precharge and keeper device connected to a precharge node. The dynamic evaluation circuit includes control logic providing a control input to the combined precharge and keeper device. The combined precharge and keeper device responsive to the control input holds the precharge node precharged when the precharge node is not discharged early in an evaluate cycle.Type: GrantFiled: April 24, 2015Date of Patent: July 19, 2016Assignee: International Business Machines CorporationInventors: Anthony G. Aipperspach, Derick G. Behrends, Todd A. Christensen, Jesse D. Smith
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Publication number: 20160182052Abstract: A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input signal. The level-shifting latch circuit also includes a first latch, having a first node and a second node, for storing the input signal in the first voltage domain, and a second latch, having a third node and a fourth node, for storing the input signal in the second voltage domain. In addition, the level-shifting circuit also includes a first switching element which provides a path to transfer a low voltage at the first node to the third node, and a second switching element which provides a path to transfer a low voltage at the second node to the fourth node.Type: ApplicationFiled: December 23, 2014Publication date: June 23, 2016Inventors: Anthony G. Aipperspach, Steven J. Baumgartner, Charles P. Geer, David P. Paulsen, David W. Siljenberg, Alan P. Wagstaff
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Publication number: 20160182053Abstract: A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input signal. The level-shifting latch circuit also includes a first latch, having a first node and a second node, for storing the input signal in the first voltage domain, and a second latch, having a third node and a fourth node, for storing the input signal in the second voltage domain. In addition, the level-shifting circuit also includes a first switching element which provides a path to transfer a low voltage at the first node to the third node, and a second switching element which provides a path to transfer a low voltage at the second node to the fourth node.Type: ApplicationFiled: December 24, 2014Publication date: June 23, 2016Inventors: Anthony G. Aipperspach, Steven J. Baumgartner, Charles P. Geer, David P. Paulsen, David W. Siljenberg, Alan P. Wagstaff
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Publication number: 20160180009Abstract: A method and circuit for implementing enhanced performance dynamic evaluation, and a design structure on which the subject circuit resides are provided. The dynamic evaluation circuit includes a combined precharge and keeper device connected to a precharge node. The dynamic evaluation circuit includes control logic providing a control input to the combined precharge and keeper device. The combined precharge and keeper device responsive to the control input holds the precharge node precharged when the precharge node is not discharged early in an evaluate cycle.Type: ApplicationFiled: April 24, 2015Publication date: June 23, 2016Inventors: Anthony G. Aipperspach, Derick G. Behrends, Todd A. Christensen, Jesse D. Smith
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Publication number: 20160180004Abstract: A method and circuit for implementing enhanced performance dynamic evaluation, and a design structure on which the subject circuit resides are provided. The dynamic evaluation circuit includes a combined precharge and keeper device connected to a precharge node. The dynamic evaluation circuit includes control logic providing a control input to the combined precharge and keeper device. The combined precharge and keeper device responsive to the control input holds the precharge node precharged when the precharge node is not discharged early in an evaluate cycle.Type: ApplicationFiled: December 18, 2014Publication date: June 23, 2016Inventors: Anthony G. Aipperspach, Derick G. Behrends, Todd A. Christensen, Jesse D. Smith