Patents by Inventor Anthony G. Domenicucci
Anthony G. Domenicucci has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Method of fabricating a device using low temperature anneal processes, a device and design structure
Patent number: 8490029Abstract: A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.Type: GrantFiled: March 15, 2012Date of Patent: July 16, 2013Assignee: International Business Machines CorporationInventors: Anthony G. Domenicucci, Terence L. Kane, Shreesh Narasimha, Karen A. Nummy, Viorel Ontalus, Yun-Yu Wang -
Patent number: 8343825Abstract: A method of forming a semiconductor device includes implanting an amorphizing species into a crystalline semiconductor substrate, the substrate having a transistor gate structure formed thereupon. Carbon is implanted into amorphized regions of the substrate, with specific implant conditions tailored such that the peak concentration of carbon species coincides with the end of the stacking faults, where the stacking faults are created during the recrystallization anneal. The implanted carbon pins partial dislocations so as to prevent the dislocations from disassociating from the end of the stacking faults and moving to a region in the substrate directly below the transistor gate structure. This removes the defects, which cause device leakage fail.Type: GrantFiled: January 19, 2011Date of Patent: January 1, 2013Assignee: International Business Machines CorporationInventors: Anthony G. Domenicucci, Shreesh Narasimha, Karen A. Nummy, Viorel C. Ontalus, Yun-Yu Wang
-
Method of fabricating a device using low temperature anneal processes, a device and design structure
Patent number: 8236709Abstract: A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.Type: GrantFiled: July 29, 2009Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Anthony G. Domenicucci, Terence L. Kane, Shreesh Narasimha, Karen A. Nummy, Viorel Ontalus, Yun-Yu Wang -
Patent number: 8227792Abstract: Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.Type: GrantFiled: February 14, 2008Date of Patent: July 24, 2012Assignee: International Business Machines CorporationInventors: Paul D. Agnello, Stephen W. Bedell, Robert H. Dennard, Anthony G. Domenicucci, Keith E. Fogel, Devendra K. Sadana
-
Publication number: 20120184075Abstract: A method of forming a semiconductor device includes implanting an amorphizing species into a crystalline semiconductor substrate, the substrate having a transistor gate structure formed thereupon. Carbon is implanted into amorphized regions of the substrate, with specific implant conditions tailored such that the peak concentration of carbon species coincides with the end of the stacking faults, where the stacking faults are created during the recrystallization anneal. The implanted carbon pins partial dislocations so as to prevent the dislocations from disassociating from the end of the stacking faults and moving to a region in the substrate directly below the transistor gate structure. This removes the defects, which cause device leakage fail.Type: ApplicationFiled: January 19, 2011Publication date: July 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony G. Domenicucci, Shreesh Narasimha, Karen A. Nummy, Viorel C. Ontalus, Yun-Yu Wang
-
METHOD OF FABRICATING A DEVICE USING LOW TEMPERATURE ANNEAL PROCESSES, A DEVICE AND DESIGN STRUCTURE
Publication number: 20120180010Abstract: A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.Type: ApplicationFiled: March 15, 2012Publication date: July 12, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony G. DOMENICUCCI, Terence L. Kane, Shreesh Narasimha, Karen A. Nummy, Viorel Ontalus, Yun-Yu Wang -
Patent number: 8021982Abstract: A method is provided for forming a metal semiconductor alloy that includes providing a deposition apparatus that includes a platinum source and a nickel source, wherein the platinum source is separate from the nickel source; positioning a substrate having a semiconductor surface in the deposition apparatus; forming a metal alloy on the semiconductor surface, wherein forming the metal alloy comprises a deposition stage in which the platinum source deposits platinum to the semiconductor surface at an initial rate at an initial period that is greater than a final rate at a final period of the deposition stage, and the nickel source deposits nickel to the semiconductor surface; and annealing the metal alloy to react the nickel and platinum with the semiconductor substrate to provide a nickel platinum semiconductor alloy.Type: GrantFiled: September 21, 2009Date of Patent: September 20, 2011Assignees: International Business Machines Corporation, Samsung Electronics Co., Ltd., Infineon Technologies AGInventors: Oh-Jung Kwon, Anthony G. Domenicucci, O Sung Kwon, Jin-Woo Choi
-
Patent number: 8021971Abstract: An integrated circuit is provided including a narrow gate stack having a width less than or equal to 65 nm, including a silicide region comprising Pt segregated in a region of the silicide away from the top surface of the silicide and towards an lower portion defined by a pulldown height of spacers on the sidewalls of the gate conductor. In a preferred embodiment, the spacers are pulled down prior to formation of the silicide. The silicide is first formed by a formation anneal, at a temperature in the range 250° C. to 450° C. Subsequently, a segregation anneal at a temperature in the range 450° C. to 550° C. The distribution of the Pt along the vertical length of the silicide layer has a peak Pt concentration within the segregated region, and the segregated Pt region has a width at half the peak Pt concentration that is less than 50% of the distance between the top surface of the silicide layer and the pulldown spacer height.Type: GrantFiled: November 4, 2009Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventors: Anthony G. Domenicucci, Christian Lavoie, Ahmet S. Ozcan
-
Patent number: 7956417Abstract: Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a <110> crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the <110> crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.Type: GrantFiled: July 20, 2010Date of Patent: June 7, 2011Assignee: International Business Machines CorporationInventors: Yun-Yu Wang, Christopher D. Sheraw, Anthony G. Domenicucci, Linda Black, Judson R. Holt, David M. Fried
-
Publication number: 20110101472Abstract: An integrated circuit is provided including a narrow gate stack having a width less than or equal to 65 nm, including a silicide region comprising Pt segregated in a region of the silicide away from the top surface of the silicide and towards an lower portion defined by a pulldown height of spacers on the sidewalls of the gate conductor. In a preferred embodiment, the spacers are pulled down prior to formation of the silicide. The silicide is first formed by a formation anneal, at a temperature in the range 250° C. to 450° C. Subsequently, a segregation anneal at a temperature in the range 450° C. to 550° C. The distribution of the Pt along the vertical length of the silicide layer has a peak Pt concentration within the segregated region, and the segregated Pt region has a width at half the peak Pt concentration that is less than 50% of the distance between the top surface of the silicide layer and the pulldown spacer height.Type: ApplicationFiled: November 4, 2009Publication date: May 5, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony G. Domenicucci, Christian Lavoie, Ahmet S. Ozcan
-
Publication number: 20110070732Abstract: A method is provided for forming a metal semiconductor alloy that includes providing a deposition apparatus that includes a platinum source and a nickel source, wherein the platinum source is separate from the nickel source; positioning a substrate having a semiconductor surface in the deposition apparatus; forming a metal alloy on the semiconductor surface, wherein forming the metal alloy comprises a deposition stage in which the platinum source deposits platinum to the semiconductor surface at an initial rate at an initial period that is greater than a final rate at a final period of the deposition stage, and the nickel source deposits nickel to the semiconductor surface; and annealing the metal alloy to react the nickel and platinum with the semiconductor substrate to provide a nickel platinum semiconductor alloy.Type: ApplicationFiled: September 21, 2009Publication date: March 24, 2011Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, INFINEON TECHNOLOGIES NORTH AMERICAN CORP., SAMSUNG ELECTRONICSInventors: Oh-Jung Kwon, Anthony G. Domenicucci, O Sung Kwon, Jin-Woo Choi
-
Method of Fabricating a Device Using Low Temperature Anneal Processes, a Device and Design Structure
Publication number: 20110027956Abstract: A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.Type: ApplicationFiled: July 29, 2009Publication date: February 3, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony G. DOMENICUCCI, Terence L. KANE, Shreesh NARASIMHA, Karen A. NUMMY, Viorel ONTALUS, Yun-Yu WANG -
Patent number: 7881093Abstract: A link portion between a first electrode and a second electrode includes a semiconductor link portion and a metal semiconductor alloy link portion comprising a first metal semiconductor alloy. An electrical pulse converts the entirety of the link portion into a second metal semiconductor alloy having a lower concentration of metal than the first metal semiconductor alloy. Due to the stoichiometric differences between the first and second metal semiconductor alloys, the link portion has a higher resistance after programming than prior to programming. The shift in electrical resistance well controlled, which is advantageously employed to as a programmable precision resistor.Type: GrantFiled: August 4, 2008Date of Patent: February 1, 2011Assignee: International Business Machines CorporationInventors: Anthony G. Domenicucci, Terence L. Kane, Michael Tenney, Yun-Yu Wang
-
Publication number: 20100283089Abstract: Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a <110> crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the <110> crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.Type: ApplicationFiled: July 20, 2010Publication date: November 11, 2010Applicants: International Business Machines Corporation, GLOBAL FOUNDRIES, INC.Inventors: Yun-Yu Wang, Christopher D. Sheraw, Anthony G. Domenicucci, Linda Black, Judson R. Holt, David M. Fried
-
Patent number: 7820501Abstract: Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a <110> crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the <110> crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.Type: GrantFiled: October 11, 2006Date of Patent: October 26, 2010Assignees: International Business Machines Corporation, GlobalFoundries, IncInventors: Yun-Yu Wang, Christopher D. Sheraw, Anthony G. Domenicucci, Linda Black, Judson R. Holt, David M. Fried
-
Patent number: 7816664Abstract: A high-quality, substantially relaxed SiGe-on-insulator substrate material which may be used as a template for strained Si is described. The substantially relaxed SiGe-on-insulator substrate includes a Si-containing substrate, an insulating region that is resistant to Ge diffusion present atop the Si-containing substrate, and a substantially relaxed SiGe layer present atop the insulating region. The insulating region includes an upper region that is comprised of a thermal oxide and the substantially relaxed SiGe layer has a thickness of about 2000 nm or less.Type: GrantFiled: June 13, 2008Date of Patent: October 19, 2010Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Huajie Chen, Anthony G. Domenicucci, Keith E. Fogel, Devendra K. Sadana
-
Patent number: 7705345Abstract: A strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET.Type: GrantFiled: January 7, 2004Date of Patent: April 27, 2010Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Kevin K. Chan, Dureseti Chidambarrao, Silke H. Christianson, Jack O. Chu, Anthony G. Domenicucci, Kam-Leung Lee, Anda C. Mocuta, John A. Ott, Qiqing C. Ouyang
-
Patent number: 7679141Abstract: A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom.Type: GrantFiled: February 7, 2008Date of Patent: March 16, 2010Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Huajie Chen, Anthony G. Domenicucci, Keith E. Fogel, Richard J. Murphy, Devendra K. Sadana
-
Publication number: 20100025819Abstract: A link portion between a first electrode and a second electrode includes a semiconductor link portion and a metal semiconductor alloy link portion comprising a first metal semiconductor alloy. An electrical pulse converts the entirety of the link portion into a second metal semiconductor alloy having a lower concentration of metal than the first metal semiconductor alloy. Due to the stoichiometric differences between the first and second metal semiconductor alloys, the link portion has a higher resistance after programming than prior to programming. The shift in electrical resistance well controlled, which is advantageously employed to as a programmable precision resistor.Type: ApplicationFiled: August 4, 2008Publication date: February 4, 2010Applicant: International Business Machines CorporationInventors: Anthony G. Domenicucci, Terence L. Kane, Michael Tenney, Yun-Yu Wang
-
Patent number: 7507988Abstract: A heterostructure is provided which includes a substantially relaxed SiGe layer present atop an insulating region that is located on a substrate. The substantially relaxed SiGe layer has a thickness of from about 2000 nm or less, a measured lattice relaxation of from about 50 to about 80% and a defect density of less than about 108 defects/cm2. A strained epitaxial Si layer is located atop the substantially relaxed SiGe layer and at least one alternating stack including a bottom relaxed SiGe layer and an top strained Si layer located on the strained epitaxial Si layer.Type: GrantFiled: January 2, 2007Date of Patent: March 24, 2009Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Huajie Chen, Anthony G. Domenicucci, Keith E. Fogel, Devendra K. Sadana