Patents by Inventor Anthony P. Bertapelli

Anthony P. Bertapelli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020164067
    Abstract: A method for selecting nearest neighbor edges to construct a 3D model from a sequence of 2D images of a scene. The method includes tracking features of the scene among successive images to generate 3D feature points. The entries of the feature point data correspond to the coordinate positions in each image which a true 3D feature point is viewed. The method also generates depth data of the features of the scene, with entries in the data corresponding to the coordinate position of the features in each image along a depth axis. The method then uses the feature track data, original images, depth data, input edge data, and visibility criteria to determine the position of vertices of the 3D model surface. The feature track data, original images, depth data, and input edge data also provide visibility information to guide the connections of the model vertices to construct the edges of the 3D model.
    Type: Application
    Filed: May 2, 2001
    Publication date: November 7, 2002
    Applicant: SynaPix
    Inventors: David B. Askey, Anthony P. Bertapelli, Curt A. Rawley
  • Patent number: 5548793
    Abstract: A system and method for arbitrating among memory requests. According to a preferred embodiment, the system comprises a global memory and a plurality of datapaths. Each datapath comprises a datapath processor for executing instructions of an instruction sequence and for providing a plurality of memory request signal types in accordance with the instructions, wherein the plurality of memory request signal types comprises instruction memory request signals, scalar memory request signals, first-in and first-out memory request signals, statistical decoder memory request signals, and block transfer memory request signals. Each datapath also comprises local memory, a global port for transferring data between the local memory and the global memory, and a dual port comprising first and second local ports for transferring data between the local memory and the datapath processor, wherein the first and second local ports permit simultaneous transfer of data between the local memory and the datapath processor.
    Type: Grant
    Filed: April 21, 1994
    Date of Patent: August 20, 1996
    Assignee: Intel Corporation
    Inventors: David L. Sprague, Kevin Harney, Eiichi Kowashi, Michael Keith, Allen H. Simon, Gregory M. Papadopoulos, Walter P. Hays, George F. Salem, Shih-Wei Shiue, Anthony P. Bertapelli, Vitaly H. Shilman
  • Patent number: 5530884
    Abstract: A method and apparatus for processing data. According to a preferred embodiment, the apparatus comprises a plurality of datapaths, each datapath comprising datapath processor, and a statistical decoder input channel device. The statistical decoder input channel device prefetches variable length encoded data from a variable length encoded data source in response to a request by a program running on a datapath processor of a datapath of the plurality of datapaths. The statistical decoder input channel device comprises a statistical decoder processor and memory for decoding the variable length encoded data to provide fixed length decoded data, and a transmission output channel for transmitting the fixed length decoded data to the datapath.
    Type: Grant
    Filed: April 21, 1994
    Date of Patent: June 25, 1996
    Assignee: Intel Corporation
    Inventors: David L. Sprague, Kevin Harney, Eiichi Kowashi, Michael Keith, Allen H. Simon, Gregory M. Papadopoulos, Walter P. Hays, George F. Salem, Shih-Wei Shiue, Anthony P. Bertapelli, Vitaly H. Shilman
  • Patent number: 5517665
    Abstract: A system and method for processing data. According to a preferred embodiment, the system comprises a global memory and a plurality of datapaths. Each datapath comprises a datapath processor for executing instructions of an instruction sequence and for providing a plurality of memory request signal types in accordance with the instructions, local memory, a global port for transferring data between the local memory and the global memory, and a dual port comprising first and second local ports for transferring data between the local memory and the datapath processor, wherein the first and second local ports permit simultaneous transfer of data between the local memory and the datapath processor.
    Type: Grant
    Filed: April 21, 1994
    Date of Patent: May 14, 1996
    Assignee: Intel Corporation
    Inventors: David L. Sprague, Kevin Harney, Eiichi Kowashi, Michael Keith, Allen H. Simon, Gregory M. Papadopoulos, Walter P. Hays, George F. Salem, Shih-Wei Shiue, Anthony P. Bertapelli, Vitaly H. Shilman
  • Patent number: 5430854
    Abstract: A data processing system having execution units for executing instruction sequences determines at least two conditionals in accordance with the instructions and sets respective flags according to the determined conditionals. These flags are stored and later retrieved sequentially and the execution unit executes selected instructions of the instruction sequence according to the sequentially retrieved mask flags. These masked flags may be stored sequentially in a stack for sequential retrieval at a later time.
    Type: Grant
    Filed: October 27, 1993
    Date of Patent: July 4, 1995
    Inventors: David L. Sprague, Kevin Harney, Eiichi Kowashi, Michael Keith, Allen H. Simon, Michael Papadopoulos, Walter P. Hays, George F. Salem, Shih-Wei Shiue, Anthony P. Bertapelli, Vitaly H. Shilman