Patents by Inventor Anton Belov

Anton Belov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10437956
    Abstract: A method for performing graph-based static timing analysis comprises reading in a design of an integrated circuit having a subset of timing paths, each timing path of the subset having a common point, wherein the common point is identical for all timing paths of the subset. The method comprises initiating a timing signal at the common point, the timing signal propagating along a plurality of timing arcs of the subset. The timing signal has a plurality of attributes varying with the propagation including a depth value and/or a distance value. The method comprises determining a derating factor for a delay of at least one of the plurality of timing arcs depending on the depth and/or the distance value of the timing signal at a pin of said at least one timing arc, and generating a timing report based on the derating factor.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: October 8, 2019
    Assignee: Synopsys, Inc.
    Inventors: Adrian Wrixon, Anton Belov, Maurice Keller, Paul Frain
  • Patent number: 10002225
    Abstract: A method for performing static timing analysis of an integrated circuit design, wherein at least two timing paths share a shared node comprises propagating along the at least two timing paths a plurality of timing signals characterized by a set of timing parameters and determining respective values of the timing parameters at the shared node. Subsets of timing signals are defined based on relations between the determined parameter values of different timing signals. For each of the subsets representative parameter values are identified and a merged timing signal is propagated from the shared node at least partially along the at least two timing paths. Therein the merged timing signal has at the shared node the representative parameter values of the subset. The method also comprises generating timing data based on the merged timing signals and storing the timing data.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: June 19, 2018
    Assignee: Synopsys, Inc.
    Inventors: Adrian Wrixon, Anton Belov, Maurice Keller, Richard Moloney, Himanshu Dadheech
  • Publication number: 20170235868
    Abstract: A method for performing static timing analysis of an integrated circuit design, wherein at least two timing paths share a shared node comprises propagating along the at least two timing paths a plurality of timing signals characterized by a set of timing parameters and determining respective values of the timing parameters at the shared node. Subsets of timing signals are defined based on relations between the determined parameter values of different timing signals. For each of the subsets representative parameter values are identified and a merged timing signal is propagated from the shared node at least partially along the at least two timing paths. Therein the merged timing signal has at the shared node the representative parameter values of the subset. The method also comprises generating timing data based on the merged timing signals and storing the timing data.
    Type: Application
    Filed: February 12, 2016
    Publication date: August 17, 2017
    Inventors: Adrian Wrixon, Anton Belov, Maurice Keller, Richard Moloney, Himanshu Dadheech
  • Publication number: 20170206301
    Abstract: A method for performing graph-based static timing analysis comprises reading in a design of an integrated circuit having a subset of timing paths, each timing path of the subset having a common point, wherein the common point is identical for all timing paths of the subset. The method comprises initiating a timing signal at the common point, the timing signal propagating along a plurality of timing arcs of the subset. The timing signal has a plurality of attributes varying with the propagation including a depth value and/or a distance value. The method comprises determining a derating factor for a delay of at least one of the plurality of timing arcs depending on the depth and/or the distance value of the timing signal at a pin of said at least one timing arc, and generating a timing report based on the derating factor.
    Type: Application
    Filed: January 15, 2016
    Publication date: July 20, 2017
    Inventors: Adrian Wrixon, Anton Belov, Maurice Keller, Paul Frain