Patents by Inventor Anton Pugatschow

Anton Pugatschow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10573611
    Abstract: A semiconductor device includes a contact metal layer disposed over a semiconductor surface of a substrate, a diffusion barrier layer disposed over the contact metal layer, an inert layer disposed over the diffusion barrier layer, and a solder layer disposed over inert layer.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: February 25, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Kamil Karlovsky, Evelyn Napetschnig, Michael Ehmann, Mark James Harrison, Anton Pugatschow
  • Patent number: 10283432
    Abstract: A method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces; a mounting at least one electronic chip on the chip carrier; an electrically coupling an electrically conductive contact structure with the at least one electronic chip; and an encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: May 7, 2019
    Assignee: Infineon Technologies AG
    Inventors: Mark Pavier, Wolfram Hable, Angela Kessler, Michael Sielaff, Anton Pugatschow, Charles Rimbert-Riviere, Marco Sobkowiak
  • Publication number: 20190051624
    Abstract: A semiconductor device includes a contact metal layer disposed over a semiconductor surface of a substrate, a diffusion barrier layer disposed over the contact metal layer, an inert layer disposed over the diffusion barrier layer, and a solder layer disposed over inert layer.
    Type: Application
    Filed: October 17, 2018
    Publication date: February 14, 2019
    Inventors: Kamil Karlovsky, Evelyn Napetschnig, Michael Ehmann, Mark James Harrison, Anton Pugatschow
  • Publication number: 20190006260
    Abstract: A method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces; a mounting at least one electronic chip on the chip carrier; an electrically coupling an electrically conductive contact structure with the at least one electronic chip; and an encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant.
    Type: Application
    Filed: August 24, 2018
    Publication date: January 3, 2019
    Inventors: Mark PAVIER, Wolfram HABLE, Angela KESSLER, Michael SIELAFF, Anton PUGATSCHOW, Charles RIMBERT-RIVIERE, Marco SOBKOWIAK
  • Patent number: 10115688
    Abstract: A semiconductor device includes a contact metal layer disposed over a semiconductor surface of a substrate, a diffusion barrier layer disposed over the contact metal layer, an inert layer disposed over the diffusion barrier layer, and a solder layer disposed over inert layer.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: October 30, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Kamil Karlovsky, Evelyn Napetschnig, Michael Ehmann, Mark Harrison, Anton Pugatschow
  • Patent number: 10074590
    Abstract: A package which comprises a chip carrier, at least one electronic chip mounted on the chip carrier, an electrically conductive contact structure electrically coupled with the at least one electronic chip, and a mold-type encapsulant encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip, wherein the chip carrier comprises a thermally conductive and electrically insulating core covered on both opposing main surfaces thereof by a respective brazed electrically conductive layer.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: September 11, 2018
    Assignee: Infineon Technologies AG
    Inventors: Mark Pavier, Wolfram Hable, Angela Kessler, Michael Sielaff, Anton Pugatschow, Charles Rimbert-Riviere, Marco Sobkowiak
  • Publication number: 20160351516
    Abstract: A semiconductor device includes a contact metal layer disposed over a semiconductor surface of a substrate, a diffusion barrier layer disposed over the contact metal layer, an inert layer disposed over the diffusion barrier layer, and a solder layer disposed over inert layer.
    Type: Application
    Filed: May 29, 2015
    Publication date: December 1, 2016
    Inventors: Kamil Karlovsky, Evelyn Napetschnig, Michael Ehmann, Mark Harrison, Anton Pugatschow
  • Publication number: 20150228607
    Abstract: In various embodiments, a layer stack is provided. The layer stack may include a carrier; a first metal disposed over the carrier; a second metal disposed over the first metal; and a solder material disposed above the second metal or a material that provides contact to a solder that is supplied by an external source. The second metal may have a melting temperature of at least 1800° C. and is not or substantially not dissolved in the solder material at least one of during a soldering process and after the soldering process.
    Type: Application
    Filed: April 22, 2015
    Publication date: August 13, 2015
    Inventors: Tobias Schmidt, Evelyn Napetschnig, Franz Stueckler, Anton Pugatschow, Mark Harrison
  • Publication number: 20120068345
    Abstract: In various embodiments, a layer stack is provided. The layer stack may include a carrier; a first metal disposed over the carrier; a second metal disposed over the first metal; and a solder material disposed above the second metal or a material that provides contact to a solder that is supplied by an external source. The second metal may have a melting temperature of at least 1800° C. and is not or substantially not dissolved in the solder material at least one of during a soldering process and after the soldering process.
    Type: Application
    Filed: September 16, 2010
    Publication date: March 22, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Tobias Schmidt, Evelyn Napetschnig, Franz Stueckler, Anton Pugatschow