Patents by Inventor Antonia R. Pelella

Antonia R. Pelella has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8325549
    Abstract: A global to local bit line interface circuit for domino SRAM devices includes a pair of complementary global write bit lines in selective communication with an array of SRAM cells through local write bit lines, the global write bit lines configured to write a selected SRAM cell with data presented on a pair of write data input lines; a pair of complementary global read bit lines in selective communication with the array through local read bit lines, the global read bit lines configured to read data stored in a selected cell and present the read data on a pair of read data output lines; and write control logic configured to control precharging of the global write bit lines independently with respect to the global read bit lines, and wherein a pulse width of write data on the global write bit lines is determined only by a global column select signal.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: December 4, 2012
    Assignee: International Business Machines Corporation
    Inventors: Yuen Hung Chan, Antonia R. Pelella
  • Patent number: 8325543
    Abstract: A global to local bit line interface circuit for domino SRAM devices includes a pair of complementary global write bit lines in selective communication with an array of SRAM cells through corresponding local write bit lines, the complementary global write bit lines configured to write a selected SRAM cell with data presented on a pair of complementary write data input lines; a pair of complementary global read bit lines in selective communication with the array of SRAM cells through corresponding local read bit lines, the complementary global read bit lines configured to read data stored in a selected SRAM cell and present the read data on a pair of complementary read data output lines; and blocking logic configured to prevent, during a write operation, propagation of stored data from the SRAM cells out on the complementary read data output lines prior to completion of the write operation.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: December 4, 2012
    Assignee: International Business Machines Corporation
    Inventors: Yuen Hung Chan, Antonia R. Pelella
  • Publication number: 20110211400
    Abstract: A global to local bit line interface circuit for domino SRAM devices includes a pair of complementary global write bit lines in selective communication with an array of SRAM cells through corresponding local write bit lines, the complementary global write bit lines configured to write a selected SRAM cell with data presented on a pair of complementary write data input lines; a pair of complementary global read bit lines in selective communication with the array of SRAM cells through corresponding local read bit lines, the complementary global read bit lines configured to read data stored in a selected SRAM cell and present the read data on a pair of complementary read data output lines; and blocking logic configured to prevent, during a write operation, propagation of stored data from the SRAM cells out on the complementary read data output lines prior to completion of the write operation.
    Type: Application
    Filed: February 26, 2010
    Publication date: September 1, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yuen Hung Chan, Antonia R. Pelella
  • Publication number: 20110211401
    Abstract: A global to local bit line interface circuit for domino SRAM devices includes a pair of complementary global write bit lines in selective communication with an array of SRAM cells through local write bit lines, the global write bit lines configured to write a selected SRAM cell with data presented on a pair of write data input lines; a pair of complementary global read bit lines in selective communication with the array through local read bit lines, the global read bit lines configured to read data stored in a selected cell and present the read data on a pair of read data output lines; and write control logic configured to control precharging of the global write bit lines independently with respect to the global read bit lines, and wherein a pulse width of write data on the global write bit lines is determined only by a global column select signal.
    Type: Application
    Filed: February 26, 2010
    Publication date: September 1, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yuen Hung Chan, Antonia R. Pelella