Abstract: A die has a positional location in a wafer defined by first and second coordinates, the first and second coordinates identifying a respective horizontal and vertical location where the die was formed. An index formed on the die has a first comb structure of a first contiguous arrangement of first dots, and a second comb structure of a second contiguous arrangement of second dots. A first marker at a selected one of the first dots indicates a first digit of the first coordinate, and a first additional marker at a selected one of the first dots indicates a second digit of the first coordinate. A second marker at a selected one of the second dots indicates a first digit of the second coordinate, and a second additional marker at a selected one of the second dots indicates a second digit of the second coordinate.

Abstract: A die has a positional location in a wafer defined by first and second coordinates, the first and second coordinates identifying a respective horizontal and vertical location where the die was formed. An index formed on the die has a first comb structure of a first contiguous arrangement of first dots, and a second comb structure of a second contiguous arrangement of second dots. A first marker at a selected one of the first dots indicates a first digit of the first coordinate, and a first additional marker at a selected one of the first dots indicates a second digit of the first coordinate. A second marker at a selected one of the second dots indicates a first digit of the second coordinate, and a second additional marker at a selected one of the second dots indicates a second digit of the second coordinate.

Abstract: A multilevel interconnect structure for a semiconductor device includes an intermetal dielectric layer with funnel-shaped connecting vias. The funnel-shaped connecting vias are provided in connection with systems exhibiting submicron spacings. The architecture of the multilevel interconnect structure provides a low resistance connecting via.

Abstract: A solution for indexing electronic devices includes corresponding electronic device including a die integrating an electronic circuit, the die having at least one index including a reference defining an ordered alignment of a plurality of locations on the die and a marker for defining a value of the index according to an arrangement of the marker with respect to the reference. In one embodiment, the marker includes a plurality of markers each one arranged at a selected one of the locations, the selected location of the marker defining a value of a digit associated with a corresponding power of a base higher than 2 within a number in a positional notation in the base representing the value of the index.

Abstract: An embodiment of an electronic device integrated in a chip of semiconductor material and an embodiment of a corresponding production method are proposed. The electronic device includes a capacitor having a first conductive plate, a second conductive plate, and an insulating layer for insulating the first plate from the second plate. In an embodiment of the disclosure, at least a selected one between the first plate and the second plate has a non-uniform thickness.

Abstract: A multilevel interconnect structure for a semiconductor device includes an intermetal dielectric layer with funnel-shaped connecting vias. The funnel-shaped connecting vias are provided in connection with systems exhibiting submicron spacings. The architecture of the multilevel interconnect structure provides a low resistance connecting via.

Abstract: A multilevel interconnect structure for a semiconductor device includes an intermetal dielectric layer with funnel-shaped connecting vias. The funnel-shaped connecting vias are provided in connection with systems exhibiting submicron spacings. The architecture of the multilevel interconnect structure provides a low resistance connecting via.

Abstract: A multilevel interconnect structure for a semiconductor device includes an intermetal dielectric layer with funnel-shaped connecting vias. The funnel-shaped connecting vias are provided in connection with systems exhibiting submicron spacings. The architecture of the multilevel interconnect structure provides a low resistance connecting via.

Abstract: A multilevel interconnect structure for a semiconductor device includes an intermetal dielectric layer with funnel-shaped connecting vias. The funnel-shaped connecting vias are provided in connection with systems exhibiting submicron spacings. The architecture of the multilevel interconnect structure provides a low resistance connecting via.

Abstract: A solution for indexing electronic devices includes corresponding electronic device including a die integrating an electronic circuit, the die having at least one index including a reference defining an ordered alignment of a plurality of locations on the die and a marker for defining a value of the index according to an arrangement of the marker with respect to the reference. In one embodiment, the marker includes a plurality of markers each one arranged at a selected one of the locations, the selected location of the marker defining a value of a digit associated with a corresponding power of a base higher than 2 within a number in a positional notation in the base representing the value of the index.

Abstract: An embodiment of an electronic device integrated in a chip of semiconductor material and an embodiment of a corresponding production method are proposed. The electronic device includes a capacitor having a first conductive plate, a second conductive plate, and an insulating layer for insulating the first plate from the second plate. In an embodiment of the invention, at least a selected one between the first plate and the second plate has a non-uniform thickness.

Abstract: In a body of semiconductor material, a field region separates a first active area and a second active area. A drain region is formed in the first active area; a body region is formed in the second active area and accommodates a source region. A body-contact region is formed inside the source region and extends from the surface as far as the body region. An insulating layer extends on top of the surface and accommodates a plurality of metal contacts, which extend as far as the drain region, the source region and the body-contact region. The body-contact region is self-aligned to a respective contact.

Abstract: In a body of semiconductor material, a field region separates a first active area and a second active area. A drain region is formed in the first active area; a body region is formed in the second active area and accommodates a source region. A body-contact region is formed inside the source region and extends from the surface as far as the body region. An insulating layer extends on top of the surface and accommodates a plurality of metal contacts, which extend as far as the drain region, the source region and the body-contact region. The body-contact region is self-aligned to a respective contact.

Abstract: In a body of semiconductor material, a field region separates a first active area and a second active area. A drain region is formed in the first active area; a body region is formed in the second active area and accommodates a source region. A body-contact region is formed inside the source region and extends from the surface as far as the body region. An insulating layer extends on top of the surface and accommodates a plurality of metal contacts, which extend as far as the drain region, the source region and the body-contact region. The body-contact region is self-aligned to a respective contact.