Patents by Inventor Antonio Maria Borneo
Antonio Maria Borneo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8269781Abstract: A system for decoding a stream of compressed digital video images comprises a graphics accelerator for reading the stream of compressed digital video images, creating, starting from said stream of compressed digital video images, three-dimensional scenes to be rendered, and converting the three-dimensional scenes to be rendered into decoded video images. The graphics accelerator is preferentially configured as pipeline selectively switchable between operation in a graphics context and operation for decoding the stream of video images. The graphics accelerator is controllable during operation for decoding the stream of compressed digital video images via a set of application programming interfaces comprising, in addition to new APIs, also standard APIs for operation of the graphics accelerator in a graphics context.Type: GrantFiled: December 22, 2008Date of Patent: September 18, 2012Assignee: STMicroelectronics S.r.l.Inventors: Danilo Pau, Antonio Maria Borneo, Daniele Lavigna
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Patent number: 8176478Abstract: Programs having a given instruction-set architecture are executed on a multiprocessor system comprising a plurality of processors, for example of a VLIW type, each of said processors being able to execute, at each processing cycle, a respective maximum number of instructions. The instructions are compiled as instruction words of given length executable on a first processor. At least some of the instruction words of given length are converted into modified-instruction words executable on a second processor. The operation of modifying comprises in turn at least one operation chosen in the group consisting of: splitting the instruction words into modified-instruction words; and entering no-operation instructions in the modified-instruction words.Type: GrantFiled: June 27, 2008Date of Patent: May 8, 2012Assignee: STMicroelectronics S.r.lInventors: Antonio Maria Borneo, Fabrizio Simone Rovati, Danilo Pietro Pau
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Patent number: 7769922Abstract: A processing system for accessing first and second data types. The first data type is data supplied from a peripheral and the second data type is randomly accessible data held in a data memory. The processing system includes: a processor for executing instructions; a stream register unit connected to supply data from the peripheral to the processor; and a FIFO. The FIFO is connected to receive data from the peripheral and connected to the stream register unit by a communication path, along which the received data can be supplied from the FIFO to the stream register unit. The Processing system also includes a memory bus connected between the data memory and the processor, across which the processor can access the randomly accessible data.Type: GrantFiled: October 30, 2003Date of Patent: August 3, 2010Assignee: STMicroelectronics (R&D) Ltd.Inventors: Mark Owen Homewood, Antonio Maria Borneo
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Patent number: 7617494Abstract: The program to be executed is compiled by translating it into native instructions of the instruction-set architecture of the processor system, organizing the instructions deriving from the translation of the program into respective bundles in an order of successive bundles, each bundle grouping together instructions adapted to be executed in parallel by the processor system. The bundles of instructions are ordered into respective sub-bundles, said sub-bundles identifying a first set of instructions, which must be executed before the instructions belonging to the next bundle of said order, and a second set of instructions, which can be executed both before and in parallel with respect to the instructions belonging to said subsequent bundle of said order.Type: GrantFiled: July 1, 2003Date of Patent: November 10, 2009Assignee: STMicroelectronics S.r.l.Inventors: Fabrizio Simone Rovati, Antonio Maria Borneo, Danilo Pietro Pau
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Publication number: 20090160866Abstract: A system for decoding a stream of compressed digital video images comprises a graphics accelerator for reading the stream of compressed digital video images, creating, starting from said stream of compressed digital video images, three-dimensional scenes to be rendered, and converting the three-dimensional scenes to be rendered into decoded video images. The graphics accelerator is preferentially configured as pipeline selectively switchable between operation in a graphics context and operation for decoding the stream of video images. The graphics accelerator is controllable during operation for decoding the stream of compressed digital video images via a set of application programming interfaces comprising, in addition to new APIs, also standard APIs for operation of the graphics accelerator in a graphics context.Type: ApplicationFiled: December 22, 2008Publication date: June 25, 2009Applicant: STMICROELECTRONICS S.R.L.Inventors: Danilo Pau, Antonio Maria Borneo, Daniele Lavigna
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Publication number: 20080270769Abstract: Programs having a given instruction-set architecture are executed on a multiprocessor system comprising a plurality of processors, for example of a VLIW type, each of said processors being able to execute, at each processing cycle, a respective maximum number of instructions. The instructions are compiled as instruction words of given length executable on a first processor. At least some of the instruction words of given length are converted into modified-instruction words executable on a second processor. The operation of modifying comprises in turn at least one operation chosen in the group consisting of: splitting the instruction words into modified-instruction words; and entering no-operation instructions in the modified-instruction words.Type: ApplicationFiled: June 27, 2008Publication date: October 30, 2008Applicant: STMicroelectronics S.r.l.Inventors: Antonio Maria Borneo, Fabrizio Simone Rovati, Danilo Pietro Pau
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Patent number: 7395532Abstract: Programs having a given instruction-set architecture are executed on a multiprocessor system comprising a plurality of processors, for example of a VLIW type, each of said processors being able to execute, at each processing cycle, a respective maximum number of instructions. The instructions are compiled as instruction words of given length executable on a first processor. At least some of the instruction words of given length are converted into modified-instruction words executable on a second processor. The operation of modifying comprises in turn at least one operation chosen in the group consisting of: splitting the instruction words into modified-instruction words; and entering no-operation instructions in the modified-instruction words.Type: GrantFiled: July 1, 2003Date of Patent: July 1, 2008Assignee: STMicroelectronics S.r.l.Inventors: Antonio Maria Borneo, Fabrizio Simone Rovati, Danilo Pietro Pau
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Patent number: 7243213Abstract: A procedure for translating ARM instructions of a first set into instructions of a second set for execution on an LX processor comprising a core provides a first set of registers corresponding to the ARM instructions and a second set of registers corresponding to the instructions that can be executed on the LX processor. Each register of the first set is mapped in a corresponding register of the second set designed to emulate the behavior of the first register, obtaining a unique independent translation of the first set into the second set. The translation is performed by a translation device external to the LX core without altering the core, and the translation operating without accessing resources of the core, by the translating device intercepting accesses of the core to the storage area reserved to the ARM instructions.Type: GrantFiled: February 10, 2004Date of Patent: July 10, 2007Assignee: STMicroelectronics S.r.l.Inventors: Andrea Pagni, Fabrizio Lucini, Danilo Pietro Pau, Antonio Maria Borneo, Vittorio Zaccaria
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Publication number: 20040225869Abstract: A procedure for translating ARM instructions of a first set into instructions of a second set for execution on an LX processor comprising a core provides a first set of registers corresponding to the ARM instructions and a second set of registers corresponding to the instructions that can be executed on the LX processor. Each register of the first set is mapped in a corresponding register of the second set designed to emulate the behavior of the first register, obtaining a unique independent translation of the first set into the second set. The translation is performed by a translation device external to the LX core without altering the core, and the translation operating without accessing resources of the core, by the translating device intercepting accesses of the core to the storage area reserved to the ARM instructions.Type: ApplicationFiled: February 10, 2004Publication date: November 11, 2004Applicant: STMicroelectronics S.r.I.Inventors: Andrea Pagni, Fabrizio Lucini, Danilo Pietro Pau, Antonio Maria Borneo, Vittorio Zaccaria
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Publication number: 20040139250Abstract: A processing system for accessing first and second data types. The first data type is data supplied from a peripheral and the second data type is randomly accessible data held in a data memory. The processing system includes a processor for executing instructions; a stream register unit connected to supply data from the peripheral to the processor; a FIFO connected to receive data from the peripheral and connected to the stream register unit by a communication path, along which the said data can be supplied from the FIFO to the stream register unit; and a memory bus connected between the data memory and the processor, across which the processor can access the randomly accessible data.Type: ApplicationFiled: October 30, 2003Publication date: July 15, 2004Inventors: Mark Own Homewood, Antonio Maria Borneo
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Publication number: 20040059894Abstract: The program to be executed is compiled by translating it into native instructions of the instruction-set architecture of the processor system, organizing the instructions deriving from the translation of the program into respective bundles in an order of successive bundles, each bundle grouping together instructions adapted to be executed in parallel by the processor system. The bundles of instructions are ordered into respective sub-bundles, said sub-bundles identifying a first set of instructions, which must be executed before the instructions belonging to the next bundle of said order, and a second set of instructions, which can be executed both before and in parallel with respect to the instructions belonging to said subsequent bundle of said order.Type: ApplicationFiled: July 1, 2003Publication date: March 25, 2004Applicant: STMicroelectronics S.r.I.Inventors: Fabrizio Simone Rovati, Antonio Maria Borneo, Danilo Pietro Pau
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Publication number: 20040054882Abstract: Programs having a given instruction-set architecture are executed on a multiprocessor system comprising a plurality of processors, for example of a VLIW type, each of said processors being able to execute, at each processing cycle, a respective maximum number of instructions. The instructions are compiled as instruction words of given length executable on a first processor. At least some of the instruction words of given length are converted into modified-instruction words executable on a second processor. The operation of modifying comprises in turn at least one operation chosen in the group consisting of: splitting the instruction words into modified-instruction words; and entering no-operation instructions in the modified-instruction words.Type: ApplicationFiled: July 1, 2003Publication date: March 18, 2004Inventors: Antonio Maria Borneo, Fabrizio Simone Rovati, Danilo Pietro Pau
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Patent number: 6657676Abstract: A method of filtering noise from digital pictures includes selecting a first set of pixels including the union of a pixel of the current picture to be filtered and a second set of pixels temporally and spatially near the pixel. A certain number of extended sums of values assumed by as many pre-established weight functions of the intensity of a selected video component on the first set of pixels is also calculated. The second set of pixels may belong to the current picture or to a preceding picture. Several noise filters for digital pictures are also provided.Type: GrantFiled: November 10, 2000Date of Patent: December 2, 2003Assignee: STMicroelectronics S.r.l.Inventors: Antonio Maria Borneo, Lanfranco Salinari
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Publication number: 20010033692Abstract: A process for estimating the noise level of a sequence of images comprises the operations of: producing a local estimate of the noise level of the said images, creating the histogram of the said estimate, deriving at least one parameter of the said histogram, and determining, by calculation or by means of an empirical relation, at least one noise level parameter on the basis of the said at least one parameter derived from the histogram. The corresponding device can be incorporated, for example, in an MPEG-2 encoder, where the parameter identifying the noise level is used for the adjustment of the internal variables of the encoding process.Type: ApplicationFiled: February 16, 2001Publication date: October 25, 2001Inventors: Antonio Maria Borneo, Lanfranco Salinari
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Patent number: 6285801Abstract: A filter reduces artifacts, such as grid noise and staircase noise, in block-coded digital images with image block boundaries. The type of filtering is determined after an estimation of the image global metrics and local metrics. For areas of the image near grid noise, the filter performs low pass filtering. For image fine details, such as edges and texture, no filtering is performed so that masking is avoided. The filter operates in intra-field mode and uses a fuzzy logic process, pixel deltas, and dual ramp generators to determine the horizontal and vertical length of a processing window surrounding an image block boundary.Type: GrantFiled: May 29, 1998Date of Patent: September 4, 2001Assignee: STMicroelectronics, Inc.Inventors: Massimo Mancuso, Antonio Maria Borneo